From 3cea36f03e8c0b02c59e00ddcd228669f7437851 Mon Sep 17 00:00:00 2001 From: Yaxun Liu Date: Tue, 21 Nov 2017 02:29:54 +0000 Subject: [AMDGPU] Fix DAGTypeLegalizer::SplitInteger for shift amount type DAGTypeLegalizer::SplitInteger uses default pointer size as shift amount constant type, which causes less performant ISA in amdgcn---amdgiz target since the default pointer type is i64 whereas the desired shift amount type is i32. This patch fixes that by using TLI.getScalarShiftAmountTy in DAGTypeLegalizer::SplitInteger. The X86 change is necessary since splitting i512 requires shifting amount of 256, which cannot be held by i8. Differential Revision: https://reviews.llvm.org/D40148 llvm-svn: 318727 --- llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp | 8 +++++--- llvm/lib/Target/X86/X86ISelLowering.h | 11 +++++++++-- 2 files changed, 14 insertions(+), 5 deletions(-) (limited to 'llvm/lib') diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp index 85154ffb14d..699081e2a5c 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp @@ -1172,9 +1172,11 @@ void DAGTypeLegalizer::SplitInteger(SDValue Op, assert(LoVT.getSizeInBits() + HiVT.getSizeInBits() == Op.getValueSizeInBits() && "Invalid integer splitting!"); Lo = DAG.getNode(ISD::TRUNCATE, dl, LoVT, Op); - Hi = DAG.getNode(ISD::SRL, dl, Op.getValueType(), Op, - DAG.getConstant(LoVT.getSizeInBits(), dl, - TLI.getPointerTy(DAG.getDataLayout()))); + Hi = + DAG.getNode(ISD::SRL, dl, Op.getValueType(), Op, + DAG.getConstant(LoVT.getSizeInBits(), dl, + TLI.getScalarShiftAmountTy( + DAG.getDataLayout(), Op.getValueType()))); Hi = DAG.getNode(ISD::TRUNCATE, dl, HiVT, Hi); } diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h index fa3fedf987c..426fb347af6 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.h +++ b/llvm/lib/Target/X86/X86ISelLowering.h @@ -18,6 +18,7 @@ #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/TargetLowering.h" +#include "llvm/Support/MathExtras.h" #include "llvm/Target/TargetOptions.h" namespace llvm { @@ -664,8 +665,14 @@ namespace llvm { void markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) const override; - MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { - return MVT::i8; + // For i512, DAGTypeLegalizer::SplitInteger needs a shift amount 256, + // which cannot be held by i8, therefore use i16 instead. In all the + // other situations i8 is sufficient. + MVT getScalarShiftAmountTy(const DataLayout &, EVT VT) const override { + MVT T = VT.getSizeInBits() >= 512 ? MVT::i16 : MVT::i8; + assert((VT.getSizeInBits() + 1) / 2 < (1U << T.getSizeInBits()) && + "Scalar shift amount type too small"); + return T; } const MCExpr * -- cgit v1.2.3