From 2945d4e91658caf48aa67ebbfe7bf47b8697f6ae Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Sun, 15 Sep 2013 15:20:54 +0000 Subject: PPC: Don't restrict lvsl generation to after type legalization The PPC backend uses a target-specific DAG combine to turn unaligned Altivec loads into a permutation-based sequence when possible. Unfortunately, the target-specific DAG combine is not always called on all loads of interest (sometimes the routines in DAGCombine call CombineTo such that the new node and users are not added to the worklist); allowing the combine to trigger early (before type legalization) mitigates this problem. Because the autovectorizers only create legal vector types, I don't expect a lot of cases where this optimization is enabled by type legalization in practice. llvm-svn: 190764 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 1 - 1 file changed, 1 deletion(-) (limited to 'llvm/lib') diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index ae046f0b7af..ddad9f82a27 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -7177,7 +7177,6 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty); if (ISD::isNON_EXTLoad(N) && VT.isVector() && TM.getSubtarget().hasAltivec() && - DCI.getDAGCombineLevel() == AfterLegalizeTypes && LD->getAlignment() < ABIAlignment) { // This is a type-legal unaligned Altivec load. SDValue Chain = LD->getChain(); -- cgit v1.2.3