From 263c6af8f3ce7bc8d1e522dbcea5962c22325839 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Mon, 1 Jul 2013 20:31:44 +0000 Subject: [mips] Increase the number of floating point control registers available to 32. Create a dedicated register class for floating point condition code registers and move FCC0 from register class CCR to the new register class. llvm-svn: 185373 --- llvm/lib/Target/Mips/MipsRegisterInfo.td | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'llvm/lib') diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.td b/llvm/lib/Target/Mips/MipsRegisterInfo.td index 36870842e6b..a5320bbff47 100644 --- a/llvm/lib/Target/Mips/MipsRegisterInfo.td +++ b/llvm/lib/Target/Mips/MipsRegisterInfo.td @@ -248,8 +248,9 @@ let Namespace = "Mips" in { def LO64 : RegisterWithSubRegs<"lo", [LO]>; } - // Status flags register - def FCR31 : Register<"31">; + // FP control registers. + foreach I = 0-31 in + def FCR#I : MipsReg<#I, ""#I>; // fcc0 register def FCC0 : MipsReg<0, "fcc0">; @@ -357,8 +358,12 @@ def AFGR64 : RegisterClass<"Mips", [f64], 64, (add def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; -// Condition Register for floating point operations -def CCR : RegisterClass<"Mips", [i32], 32, (add FCR31,FCC0)>, Unallocatable; +// FP control registers. +def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>, + Unallocatable; + +// FP condition code registers. +def FCC : RegisterClass<"Mips", [i32], 32, (add FCC0)>, Unallocatable; // Hi/Lo Registers def LORegs : RegisterClass<"Mips", [i32], 32, (add LO)>; -- cgit v1.2.3