From 0f61579602d6b923cb44b432f29e6d83b04b0945 Mon Sep 17 00:00:00 2001
From: Adrian Prantl <aprantl@apple.com>
Date: Wed, 4 Mar 2015 17:39:33 +0000
Subject: Fix DwarfExpression::AddMachineRegExpression so it doesn't read past
 the end of an expression that ends with DW_OP_plus. Caught by the ASAN build
 bots.

llvm-svn: 231260
---
 llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp | 26 ++++++++++++++-----------
 llvm/lib/IR/DebugInfo.cpp                       |  4 ++--
 2 files changed, 17 insertions(+), 13 deletions(-)

(limited to 'llvm/lib')

diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
index 86954e90b68..489e455c122 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
@@ -196,11 +196,12 @@ bool DwarfExpression::AddMachineRegExpression(DIExpression Expr,
                                               unsigned MachineReg,
                                               unsigned PieceOffsetInBits) {
   auto I = Expr.begin();
-  // Pattern-match combinations for which more efficient representations exist
-  // first.
-  if (I == Expr.end())
+  auto E = Expr.end();
+  if (I == E)
     return AddMachineRegPiece(MachineReg);
 
+  // Pattern-match combinations for which more efficient representations exist
+  // first.
   bool ValidReg = false;
   switch (*I) {
   case dwarf::DW_OP_bit_piece: {
@@ -210,20 +211,23 @@ bool DwarfExpression::AddMachineRegExpression(DIExpression Expr,
     return AddMachineRegPiece(MachineReg, SizeInBits,
                getOffsetOrZero(OffsetInBits, PieceOffsetInBits));
   }
-  case dwarf::DW_OP_plus:
+  case dwarf::DW_OP_plus: {
     // [DW_OP_reg,Offset,DW_OP_plus,DW_OP_deref] --> [DW_OP_breg,Offset].
-    if (I->getNext() == dwarf::DW_OP_deref) {
+    auto N = I->getNext();
+    if ((N != E) && (*N == dwarf::DW_OP_deref)) {
       unsigned Offset = I->getArg(1);
       ValidReg = AddMachineRegIndirect(MachineReg, Offset);
       std::advance(I, 2);
       break;
     } else
       ValidReg = AddMachineRegPiece(MachineReg);
-  case dwarf::DW_OP_deref:
-    // [DW_OP_reg,DW_OP_deref] --> [DW_OP_breg].
-    ValidReg = AddMachineRegIndirect(MachineReg);
-    ++I;
-    break;
+  }
+  case dwarf::DW_OP_deref: {
+      // [DW_OP_reg,DW_OP_deref] --> [DW_OP_breg].
+      ValidReg = AddMachineRegIndirect(MachineReg);
+      ++I;
+      break;
+  }
   default:
     llvm_unreachable("unsupported operand");
   }
@@ -232,7 +236,7 @@ bool DwarfExpression::AddMachineRegExpression(DIExpression Expr,
     return false;
 
   // Emit remaining elements of the expression.
-  AddExpression(I, Expr.end(), PieceOffsetInBits);
+  AddExpression(I, E, PieceOffsetInBits);
   return true;
 }
 
diff --git a/llvm/lib/IR/DebugInfo.cpp b/llvm/lib/IR/DebugInfo.cpp
index d44d6c9e15b..3db74fcee58 100644
--- a/llvm/lib/IR/DebugInfo.cpp
+++ b/llvm/lib/IR/DebugInfo.cpp
@@ -183,9 +183,9 @@ uint64_t DIExpression::getBitPieceSize() const {
   return getElement(getNumElements()-1);
 }
 
-DIExpression::Operand DIExpression::Operand::getNext() const {
+DIExpression::iterator DIExpression::Operand::getNext() const {
   iterator it(I);
-  return *(++it);
+  return ++it;
 }
 
 //===----------------------------------------------------------------------===//
-- 
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