From 342c3bcf110f4ce4f75f1855845e43ab1553bdb9 Mon Sep 17 00:00:00 2001
From: Sanjay Patel <spatel@rotateright.com>
Date: Tue, 11 Sep 2018 18:49:00 +0000
Subject: [InstCombine] enhance vector demanded elements to look at a vector
 select condition operand

I noticed that we were not back-propagating undef lanes to shuffle masks when we have a
shuffle that reduces the vector width. This is part of investigating/solving PR38691:
https://bugs.llvm.org/show_bug.cgi?id=38691

The DAG equivalent was proposed with:
D51696

Differential Revision: https://reviews.llvm.org/D51433

llvm-svn: 341981
---
 .../InstCombine/InstCombineSimplifyDemanded.cpp    | 23 ++++++++++++++++++++--
 1 file changed, 21 insertions(+), 2 deletions(-)

(limited to 'llvm/lib/Transforms')

diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index 78de6dfe7f4..ad636594bb7 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -1260,17 +1260,35 @@ Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, APInt DemandedElts,
     break;
   }
   case Instruction::Select: {
+    // If this is a vector select, try to transform the select condition based
+    // on the current demanded elements.
     SelectInst *Sel = cast<SelectInst>(I);
-    Value *Cond = Sel->getCondition();
+    if (Sel->getCondition()->getType()->isVectorTy()) {
+      // TODO: We are not doing anything with UndefElts based on this call.
+      // It is overwritten below based on the other select operands. If an
+      // element of the select condition is known undef, then we are free to
+      // choose the output value from either arm of the select. If we know that
+      // one of those values is undef, then the output can be undef.
+      if (Value *V = SimplifyDemandedVectorElts(Sel->getCondition(),
+                                                DemandedElts, UndefElts,
+                                                Depth + 1)) {
+        Sel->setCondition(V);
+        MadeChange = true;
+      }
+    }
 
+    // Next, see if we can transform the arms of the select.
     APInt DemandedLHS(DemandedElts), DemandedRHS(DemandedElts);
-    if (auto *CV = dyn_cast<ConstantVector>(Cond)) {
+    if (auto *CV = dyn_cast<ConstantVector>(Sel->getCondition())) {
       for (unsigned i = 0; i < VWidth; i++) {
         // isNullValue() always returns false when called on a ConstantExpr.
         // Skip constant expressions to avoid propagating incorrect information.
         Constant *CElt = CV->getAggregateElement(i);
         if (isa<ConstantExpr>(CElt))
           continue;
+        // TODO: If a select condition element is undef, we can demand from
+        // either side. If one side is known undef, choosing that side would
+        // propagate undef.
         if (CElt->isNullValue())
           DemandedLHS.clearBit(i);
         else
@@ -1291,6 +1309,7 @@ Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, APInt DemandedElts,
     }
 
     // Output elements are undefined if the element from each arm is undefined.
+    // TODO: This can be improved. See comment in select condition handling.
     UndefElts = UndefElts2 & UndefElts3;
     break;
   }
-- 
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