From 17455633c77d7bbdf7eaec852a4b6daef54b5f7f Mon Sep 17 00:00:00 2001 From: Arnold Schwaighofer Date: Sun, 2 Feb 2014 03:12:34 +0000 Subject: LoopVectorizer: Enable unrolling of conditional stores and the load/store unrolling heuristic per default Benchmarking on x86_64 (thanks Chandler!) and ARM has shown those options speed up some benchmarks while not causing any interesting regressions. llvm-svn: 200621 --- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'llvm/lib/Transforms/Vectorize') diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index 1f494922b31..930cf7799a2 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -180,16 +180,16 @@ static cl::opt LoopVectorizeWithBlockFrequency( // Runtime unroll loops for load/store throughput. static cl::opt EnableLoadStoreRuntimeUnroll( - "enable-loadstore-runtime-unroll", cl::init(false), cl::Hidden, + "enable-loadstore-runtime-unroll", cl::init(true), cl::Hidden, cl::desc("Enable runtime unrolling until load/store ports are saturated")); /// The number of stores in a loop that are allowed to need predication. static cl::opt NumberOfStoresToPredicate( - "vectorize-num-stores-pred", cl::init(0), cl::Hidden, + "vectorize-num-stores-pred", cl::init(1), cl::Hidden, cl::desc("Max number of stores to be predicated behind an if.")); static cl::opt EnableIndVarRegisterHeur( - "enable-ind-var-reg-heur", cl::init(false), cl::Hidden, + "enable-ind-var-reg-heur", cl::init(true), cl::Hidden, cl::desc("Count the induction variable only once when unrolling")); static cl::opt EnableCondStoresVectorization( -- cgit v1.2.3