From e56a2fc5e7ee74320eb0d218b0ba5c703696a80b Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 17 Apr 2018 19:35:19 +0000 Subject: [X86] Add separate scheduling class for PSADBW instruction. llvm-svn: 330204 --- llvm/lib/Target/X86/X86InstrAVX512.td | 2 +- llvm/lib/Target/X86/X86InstrMMX.td | 2 +- llvm/lib/Target/X86/X86InstrSSE.td | 6 +++--- llvm/lib/Target/X86/X86SchedBroadwell.td | 3 +-- llvm/lib/Target/X86/X86SchedHaswell.td | 3 +-- llvm/lib/Target/X86/X86SchedSandyBridge.td | 5 ++--- llvm/lib/Target/X86/X86SchedSkylakeClient.td | 5 ++--- llvm/lib/Target/X86/X86SchedSkylakeServer.td | 9 ++------- llvm/lib/Target/X86/X86Schedule.td | 1 + llvm/lib/Target/X86/X86ScheduleAtom.td | 1 + llvm/lib/Target/X86/X86ScheduleBtVer2.td | 1 + llvm/lib/Target/X86/X86ScheduleSLM.td | 1 + llvm/lib/Target/X86/X86ScheduleZnver1.td | 1 + 13 files changed, 18 insertions(+), 22 deletions(-) (limited to 'llvm/lib/Target') diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index bd718ad19e5..fb6b7b59731 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -10076,7 +10076,7 @@ multiclass avx512_psadbw_packed_all opc, SDNode OpNode, } defm VPSADBW : avx512_psadbw_packed_all<0xf6, X86psadbw, "vpsadbw", - WriteMPSAD, HasBWI>, EVEX_4V, VEX_WIG; + WritePSADBW, HasBWI>, EVEX_4V, VEX_WIG; // Transforms to swizzle an immediate to enable better matching when // memory operand isn't in the right place. diff --git a/llvm/lib/Target/X86/X86InstrMMX.td b/llvm/lib/Target/X86/X86InstrMMX.td index 5c505b0b425..8001cee027f 100644 --- a/llvm/lib/Target/X86/X86InstrMMX.td +++ b/llvm/lib/Target/X86/X86InstrMMX.td @@ -384,7 +384,7 @@ defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, WriteVecALU, 1>; defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw, - WriteVecIMul, 1>; + WritePSADBW, 1>; } defm MMX_PSIGNB : SS3I_binop_rm_int_mm<0x08, "psignb", int_x86_ssse3_psign_b, diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 5b4f29c8059..d9a279abab3 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -3370,15 +3370,15 @@ defm PMADDWD : PDI_binop_rm2<0xF5, "pmaddwd", X86vpmaddwd, v4i32, v8i16, VR128, let Predicates = [HasAVX, NoVLX_Or_NoBWI] in defm VPSADBW : PDI_binop_rm2<0xF6, "vpsadbw", X86psadbw, v2i64, v16i8, VR128, - loadv2i64, i128mem, WriteVecALU, 0>, + loadv2i64, i128mem, WritePSADBW, 0>, VEX_4V, VEX_WIG; let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in defm VPSADBWY : PDI_binop_rm2<0xF6, "vpsadbw", X86psadbw, v4i64, v32i8, VR256, - loadv4i64, i256mem, WriteVecALU, 0>, + loadv4i64, i256mem, WritePSADBW, 0>, VEX_4V, VEX_L, VEX_WIG; let Constraints = "$src1 = $dst" in defm PSADBW : PDI_binop_rm2<0xF6, "psadbw", X86psadbw, v2i64, v16i8, VR128, - memopv2i64, i128mem, WriteVecALU>; + memopv2i64, i128mem, WritePSADBW>; //===---------------------------------------------------------------------===// // SSE2 - Packed Integer Logical Instructions diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td index 4b377d76cb6..256dd897fe7 100755 --- a/llvm/lib/Target/X86/X86SchedBroadwell.td +++ b/llvm/lib/Target/X86/X86SchedBroadwell.td @@ -185,6 +185,7 @@ defm : BWWriteResPair; // Vector variable shuffl defm : BWWriteResPair; // Vector blends. defm : BWWriteResPair; // Vector variable blends. defm : BWWriteResPair; // Vector MPSAD. +defm : BWWriteResPair; // Vector PSADBW. // Vector bitwise operations. // These are often used on both floating point and integer vectors. @@ -1097,7 +1098,6 @@ def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMADDUBSWrr", "MMX_PMULHWirr", "MMX_PMULLWirr", "MMX_PMULUDQirr", - "MMX_PSADBWirr", "MUL_FPrST0", "MUL_FST0r", "MUL_FrST0", @@ -1111,7 +1111,6 @@ def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMADDUBSWrr", "(V?)PMULHW(Y?)rr", "(V?)PMULLW(Y?)rr", "(V?)PMULUDQ(Y?)rr", - "(V?)PSADBW(Y?)rr", "(V?)RCPPSr", "(V?)RCPSSr", "(V?)RSQRTPSr", diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index 045aa654a86..20c4f811e38 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -185,6 +185,7 @@ defm : HWWriteResPair; defm : HWWriteResPair; defm : HWWriteResPair; defm : HWWriteResPair; +defm : HWWriteResPair; // String instructions. @@ -2257,7 +2258,6 @@ def: InstRW<[HWWriteResGroup89], (instregex "MMX_PMADDUBSWrr", "MMX_PMULHWirr", "MMX_PMULLWirr", "MMX_PMULUDQirr", - "MMX_PSADBWirr", "MUL_FPrST0", "MUL_FST0r", "MUL_FrST0", @@ -2271,7 +2271,6 @@ def: InstRW<[HWWriteResGroup89], (instregex "MMX_PMADDUBSWrr", "(V?)PMULHW(Y?)rr", "(V?)PMULLW(Y?)rr", "(V?)PMULUDQ(Y?)rr", - "(V?)PSADBW(Y?)rr", "(V?)RCPPSr", "(V?)RCPSSr", "(V?)RSQRTPSr", diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td index 1f342458409..8e56cdabfa4 100644 --- a/llvm/lib/Target/X86/X86SchedSandyBridge.td +++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td @@ -169,6 +169,7 @@ defm : SBWriteResPair; defm : SBWriteResPair; defm : SBWriteResPair; defm : SBWriteResPair; +defm : SBWriteResPair; //////////////////////////////////////////////////////////////////////////////// // Horizontal add/sub instructions. @@ -616,9 +617,7 @@ def: InstRW<[SBWriteResGroup20], (instregex "MMX_PMADDUBSWrr", "MMX_PMULHUWirr", "MMX_PMULHWirr", "MMX_PMULLWirr", - "MMX_PMULUDQirr", - "MMX_PSADBWirr", - "(V?)PSADBWrr")>; + "MMX_PMULUDQirr")>; def SBWriteResGroup21 : SchedWriteRes<[SBPort1]> { let Latency = 3; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td index 497b3a6872e..16fce1e607e 100644 --- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td @@ -182,6 +182,7 @@ defm : SKLWriteResPair; // Vector shuffles. defm : SKLWriteResPair; // Vector blends. defm : SKLWriteResPair; // Vector variable blends. defm : SKLWriteResPair; // Vector MPSAD. +defm : SKLWriteResPair; // Vector PSADBW. // Vector bitwise operations. // These are often used on both floating point and integer vectors. @@ -858,7 +859,6 @@ def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> { def: InstRW<[SKLWriteResGroup30], (instregex "ADD_FPrST0", "ADD_FST0r", "ADD_FrST0", - "MMX_PSADBWirr", "SUBR_FPrST0", "SUBR_FST0r", "SUBR_FrST0", @@ -891,8 +891,7 @@ def: InstRW<[SKLWriteResGroup30], (instregex "ADD_FPrST0", "VPMOVZXBWYrr", "VPMOVZXDQYrr", "VPMOVZXWDYrr", - "VPMOVZXWQYrr", - "(V?)PSADBW(Y?)rr")>; + "VPMOVZXWQYrr")>; def SKLWriteResGroup31 : SchedWriteRes<[SKLPort0,SKLPort5]> { let Latency = 3; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td index 188c29abf30..09c613366ad 100755 --- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td @@ -182,6 +182,7 @@ defm : SKXWriteResPair; // Vector variable shu defm : SKXWriteResPair; // Vector blends. defm : SKXWriteResPair; // Vector variable blends. defm : SKXWriteResPair; // Vector MPSAD. +defm : SKXWriteResPair; // Vector PSADBW. // Vector bitwise operations. // These are often used on both floating point and integer vectors. @@ -1683,9 +1684,7 @@ def: InstRW<[SKXWriteResGroup32], (instregex "ADD_FPrST0", "KUNPCKBWrr", "KUNPCKDQrr", "KUNPCKWDrr", - "MMX_PSADBWirr", "PCMPGTQrr", - "PSADBWrr", "SUBR_FPrST0", "SUBR_FST0r", "SUBR_FrST0", @@ -1901,11 +1900,7 @@ def: InstRW<[SKXWriteResGroup32], (instregex "ADD_FPrST0", "VPMOVZXWQZ128rr", "VPMOVZXWQZ256rr", "VPMOVZXWQZrr", - "VPSADBWYrr", - "VPSADBWZ128rr", - "VPSADBWZ256rr", - "VPSADBWZrr", - "VPSADBWrr", + "VPSADBWZrr", // TODO: 512-bit ops require ports 0/1 to be joined. "VPTESTMBZ128rr", "VPTESTMBZ256rr", "VPTESTMBZrr", diff --git a/llvm/lib/Target/X86/X86Schedule.td b/llvm/lib/Target/X86/X86Schedule.td index cb709e9f698..dd2ffeddf49 100644 --- a/llvm/lib/Target/X86/X86Schedule.td +++ b/llvm/lib/Target/X86/X86Schedule.td @@ -111,6 +111,7 @@ defm WriteShuffle : X86SchedWritePair; // Vector shuffles. defm WriteVarShuffle : X86SchedWritePair; // Vector variable shuffles. defm WriteBlend : X86SchedWritePair; // Vector blends. defm WriteVarBlend : X86SchedWritePair; // Vector variable blends. +defm WritePSADBW : X86SchedWritePair; // Vector PSADBW. defm WriteMPSAD : X86SchedWritePair; // Vector MPSAD. // Vector bitwise operations. diff --git a/llvm/lib/Target/X86/X86ScheduleAtom.td b/llvm/lib/Target/X86/X86ScheduleAtom.td index fa398d0e785..a76cdce3883 100644 --- a/llvm/lib/Target/X86/X86ScheduleAtom.td +++ b/llvm/lib/Target/X86/X86ScheduleAtom.td @@ -240,6 +240,7 @@ defm : AtomWriteResPair; defm : AtomWriteResPair; defm : AtomWriteResPair; +defm : AtomWriteResPair; defm : AtomWriteResPair; defm : AtomWriteResPair; defm : AtomWriteResPair; // NOTE: Doesn't exist on Atom. diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td index 3e4c0a6d5e0..694d7047c0a 100644 --- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td +++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td @@ -370,6 +370,7 @@ defm : JWriteResFpuPair; defm : JWriteResFpuPair; defm : JWriteResFpuPair; defm : JWriteResFpuPair; +defm : JWriteResFpuPair; defm : JWriteResFpuPair; defm : JWriteResFpuPair; defm : JWriteResFpuPair; diff --git a/llvm/lib/Target/X86/X86ScheduleSLM.td b/llvm/lib/Target/X86/X86ScheduleSLM.td index 8e913b48a12..da4d38f4a7d 100644 --- a/llvm/lib/Target/X86/X86ScheduleSLM.td +++ b/llvm/lib/Target/X86/X86ScheduleSLM.td @@ -155,6 +155,7 @@ defm : SLMWriteResPair; defm : SLMWriteResPair; defm : SLMWriteResPair; defm : SLMWriteResPair; +defm : SLMWriteResPair; //////////////////////////////////////////////////////////////////////////////// // Horizontal add/sub instructions. diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td index dc9438c8dae..051b2e46fc5 100644 --- a/llvm/lib/Target/X86/X86ScheduleZnver1.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td @@ -226,6 +226,7 @@ defm : ZnWriteResFpuPair; defm : ZnWriteResFpuPair; defm : ZnWriteResFpuPair; defm : ZnWriteResFpuPair; +defm : ZnWriteResFpuPair; // Vector Shift Operations defm : ZnWriteResFpuPair; -- cgit v1.2.3