From d1f8bde10f0c7bb0cab5ebf6171909fa808ac2fc Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Fri, 22 Jul 2011 18:13:31 +0000 Subject: ARM assembly parsing and encoding for SMC instruction. llvm-svn: 135782 --- llvm/lib/Target/ARM/ARMInstrInfo.td | 4 ++-- llvm/lib/Target/ARM/ARMInstrThumb2.td | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'llvm/lib/Target') diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index 7b675c85327..fb822355cd6 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -1742,8 +1742,8 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { // Secure Monitor Call is a system instruction -- for disassembly only -def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt", - [/* For disassembly only; pattern left blank */]> { +def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", + []> { bits<4> opt; let Inst{23-4} = 0b01100000000000000111; let Inst{3-0} = opt; diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index 6241b31da60..287c2d94d28 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -3170,7 +3170,7 @@ def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> { // Secure Monitor Call is a system instruction -- for disassembly only // Option = Inst{19-16} -def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt", +def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", [/* For disassembly only; pattern left blank */]> { let Inst{31-27} = 0b11110; let Inst{26-20} = 0b1111111; -- cgit v1.2.3