From c8e33c5ca176e9f368a064c460fc5f910cde9477 Mon Sep 17 00:00:00 2001 From: Simon Dardis Date: Thu, 28 Sep 2017 15:24:07 +0000 Subject: [mips] Remove codegen support for branch likely instructions. This patch disables codegen support for branch likely instructions to address a potential bug. These branches were unselectable as they had the same patterns as the normal branches but came after them when ISel was concerned. The branch likely instructions were marked as having no delay slots when they have annulling delay slots. The delay slot filler does not currently handle annulling delay slot branches, so this would lead to wrong codegen if these branches were generated. Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D38169 llvm-svn: 314421 --- llvm/lib/Target/Mips/MipsInstrFPU.td | 19 +++++++++++--- llvm/lib/Target/Mips/MipsInstrInfo.td | 48 +++++++++++++++++++++++++---------- 2 files changed, 49 insertions(+), 18 deletions(-) (limited to 'llvm/lib/Target') diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td index 999e5fadb81..868183975a1 100644 --- a/llvm/lib/Target/Mips/MipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MipsInstrFPU.td @@ -215,14 +215,25 @@ class SWXC1_FT : + SDPatternOperator Op = null_frag> : InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset), !strconcat(opstr, "\t$fcc, $offset"), [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin, FrmFI, opstr>, HARDFLOAT { let isBranch = 1; let isTerminator = 1; - let hasDelaySlot = DelaySlot; + let hasDelaySlot = 1; + let Defs = [AT]; + let hasFCCRegOperand = 1; +} + +class BC1XL_FT : + InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset), + !strconcat(opstr, "\t$fcc, $offset"), [], Itin, + FrmFI, opstr>, HARDFLOAT { + let isBranch = 1; + let isTerminator = 1; + let hasDelaySlot = 1; let Defs = [AT]; let hasFCCRegOperand = 1; } @@ -619,11 +630,11 @@ def MIPS_BRANCH_T : PatLeaf<(i32 1)>; def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>, BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6; -def BC1FL : MMRel, BC1F_FT<"bc1fl", brtarget, II_BC1FL, MIPS_BRANCH_F, 0>, +def BC1FL : MMRel, BC1XL_FT<"bc1fl", brtarget, II_BC1FL>, BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6; def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>, BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6; -def BC1TL : MMRel, BC1F_FT<"bc1tl", brtarget, II_BC1TL, MIPS_BRANCH_T, 0>, +def BC1TL : MMRel, BC1XL_FT<"bc1tl", brtarget, II_BC1TL>, BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6; /// Floating Point Compare diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 50515808376..fbb8e33f40e 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -1399,27 +1399,47 @@ class SW_FT3 : + RegisterOperand RO> : InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset), !strconcat(opstr, "\t$rs, $rt, $offset"), [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], II_BCC, FrmI, opstr> { let isBranch = 1; let isTerminator = 1; - let hasDelaySlot = DelaySlot; + let hasDelaySlot = 1; + let Defs = [AT]; + bit isCTI = 1; +} + +class CBranchLikely : + InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset), + !strconcat(opstr, "\t$rs, $rt, $offset"), [], II_BCC, FrmI, opstr> { + let isBranch = 1; + let isTerminator = 1; + let hasDelaySlot = 1; let Defs = [AT]; bit isCTI = 1; } class CBranchZero : + RegisterOperand RO> : InstSE<(outs), (ins RO:$rs, opnd:$offset), !strconcat(opstr, "\t$rs, $offset"), [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], II_BCCZ, FrmI, opstr> { let isBranch = 1; let isTerminator = 1; - let hasDelaySlot = DelaySlot; + let hasDelaySlot = 1; + let Defs = [AT]; + bit isCTI = 1; +} + +class CBranchZeroLikely : + InstSE<(outs), (ins RO:$rs, opnd:$offset), + !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZ, FrmI, opstr> { + let isBranch = 1; + let isTerminator = 1; + let hasDelaySlot = 1; let Defs = [AT]; bit isCTI = 1; } @@ -1495,10 +1515,10 @@ let isCall=1, hasDelaySlot=1, isCTI=1, Defs = [RA] in { [], II_JALR, FrmR, opstr>; class BGEZAL_FT : + RegisterOperand RO> : InstSE<(outs), (ins RO:$rs, opnd:$offset), !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZAL, FrmI, opstr> { - let hasDelaySlot = DelaySlot; + let hasDelaySlot = 1; } } @@ -2011,26 +2031,26 @@ def J : MMRel, JumpFJ, FJ<2>, AdditionalRequires<[RelocNotPIC]>, IsBranch; def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>, ISA_MIPS1_NOT_32R6_64R6; def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>; -def BEQL : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>, +def BEQL : MMRel, CBranchLikely<"beql", brtarget, GPR32Opnd>, BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6; def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>; -def BNEL : MMRel, CBranch<"bnel", brtarget, setne, GPR32Opnd, 0>, +def BNEL : MMRel, CBranchLikely<"bnel", brtarget, GPR32Opnd>, BEQ_FM<21>, ISA_MIPS2_NOT_32R6_64R6; def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>, BGEZ_FM<1, 1>; -def BGEZL : MMRel, CBranchZero<"bgezl", brtarget, setge, GPR32Opnd, 0>, +def BGEZL : MMRel, CBranchZeroLikely<"bgezl", brtarget, GPR32Opnd>, BGEZ_FM<1, 3>, ISA_MIPS2_NOT_32R6_64R6; def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>, BGEZ_FM<7, 0>; -def BGTZL : MMRel, CBranchZero<"bgtzl", brtarget, setgt, GPR32Opnd, 0>, +def BGTZL : MMRel, CBranchZeroLikely<"bgtzl", brtarget, GPR32Opnd>, BGEZ_FM<23, 0>, ISA_MIPS2_NOT_32R6_64R6; def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>, BGEZ_FM<6, 0>; -def BLEZL : MMRel, CBranchZero<"blezl", brtarget, setle, GPR32Opnd, 0>, +def BLEZL : MMRel, CBranchZeroLikely<"blezl", brtarget, GPR32Opnd>, BGEZ_FM<22, 0>, ISA_MIPS2_NOT_32R6_64R6; def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>, BGEZ_FM<1, 0>; -def BLTZL : MMRel, CBranchZero<"bltzl", brtarget, setlt, GPR32Opnd, 0>, +def BLTZL : MMRel, CBranchZeroLikely<"bltzl", brtarget, GPR32Opnd>, BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6; def B : UncondBranch; @@ -2044,11 +2064,11 @@ def JALX : MMRel, JumpLink<"jalx", calltarget>, FJ<0x1D>, ISA_MIPS32_NOT_32R6_64R6; def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>, ISA_MIPS1_NOT_32R6_64R6; -def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd, 0>, +def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd>, BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6; def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>, ISA_MIPS1_NOT_32R6_64R6; -def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd, 0>, +def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd>, BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6; def BAL_BR : BAL_BR_Pseudo; -- cgit v1.2.3