From b8bbcbfcc81bb6101322c34fb4c770afb090a68c Mon Sep 17 00:00:00 2001 From: Yunzhong Gao Date: Fri, 27 Sep 2013 18:38:42 +0000 Subject: Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539 --- llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h | 3 + .../Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 3 + llvm/lib/Target/X86/X86CodeEmitter.cpp | 3 + llvm/lib/Target/X86/X86InstrFormats.td | 1 + llvm/lib/Target/X86/X86InstrInfo.td | 79 ++++++++++++++++++++++ 5 files changed, 89 insertions(+) (limited to 'llvm/lib/Target') diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h b/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h index 25d1af39387..1ef98141f82 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h +++ b/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h @@ -354,6 +354,9 @@ namespace X86II { // XOP9 - Prefix to exclude use of imm byte. XOP9 = 21 << Op0Shift, + // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions. + XOPA = 22 << Op0Shift, + //===------------------------------------------------------------------===// // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. // They are used to specify GPRs and SSE registers, 64-bit operand size, diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp index 0c9fd91e310..032c52cf852 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp @@ -665,6 +665,9 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, case X86II::XOP9: VEX_5M = 0x9; break; + case X86II::XOPA: + VEX_5M = 0xA; + break; case X86II::A6: // Bypass: Not used by VEX case X86II::A7: // Bypass: Not used by VEX case X86II::TB: // Bypass: Not used by VEX diff --git a/llvm/lib/Target/X86/X86CodeEmitter.cpp b/llvm/lib/Target/X86/X86CodeEmitter.cpp index e786ebb5f98..122d2917003 100644 --- a/llvm/lib/Target/X86/X86CodeEmitter.cpp +++ b/llvm/lib/Target/X86/X86CodeEmitter.cpp @@ -919,6 +919,9 @@ void Emitter::emitVEXOpcodePrefix(uint64_t TSFlags, case X86II::XOP9: VEX_5M = 0x9; break; + case X86II::XOPA: + VEX_5M = 0xA; + break; case X86II::A6: // Bypass: Not used by VEX case X86II::A7: // Bypass: Not used by VEX case X86II::TB: // Bypass: Not used by VEX diff --git a/llvm/lib/Target/X86/X86InstrFormats.td b/llvm/lib/Target/X86/X86InstrFormats.td index fb07ed0818b..ebe94a54f26 100644 --- a/llvm/lib/Target/X86/X86InstrFormats.td +++ b/llvm/lib/Target/X86/X86InstrFormats.td @@ -139,6 +139,7 @@ class T8XS { bits<5> Prefix = 18; } class TAXD { bits<5> Prefix = 19; } class XOP8 { bits<5> Prefix = 20; } class XOP9 { bits<5> Prefix = 21; } +class XOPA { bits<5> Prefix = 22; } class VEX { bit hasVEXPrefix = 1; } class VEX_W { bit hasVEX_WPrefix = 1; } class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; } diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index 148ac6d32cc..3b16fb02967 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -664,6 +664,7 @@ def HasFMA : Predicate<"Subtarget->hasFMA()">; def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">; def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; def HasXOP : Predicate<"Subtarget->hasXOP()">; +def HasTBM : Predicate<"Subtarget->hasTBM()">; def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">; def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">; def HasF16C : Predicate<"Subtarget->hasF16C()">; @@ -1906,6 +1907,84 @@ let Predicates = [HasBMI2] in { int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W; } +//===----------------------------------------------------------------------===// +// TBM Instructions +// +let isAsmParserOnly = 1, Predicates = [HasTBM], Defs = [EFLAGS] in { + +multiclass tbm_ternary_imm_intr opc, RegisterClass RC, string OpcodeStr, + X86MemOperand x86memop, PatFrag ld_frag, + Intrinsic Int> { + def rr : Ii32, + XOP, XOPA, VEX; + def mr : Ii32, + XOP, XOPA, VEX; +} + +defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32, + int_x86_tbm_bextri_u32>; +defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64, + int_x86_tbm_bextri_u64>, VEX_W; + +multiclass tbm_binary_rm opc, Format FormReg, Format FormMem, + RegisterClass RC, string OpcodeStr, + X86MemOperand x86memop, PatFrag ld_frag, + Intrinsic Int> { + def rr : I, + XOP, XOP9, VEX_4V; + def rm : I, + XOP, XOP9, VEX_4V; +} + +multiclass tbm_binary_intr opc, string OpcodeStr, + Format FormReg, Format FormMem, + Intrinsic Int32, Intrinsic Int64> { + defm _32 : tbm_binary_rm; + defm _64 : tbm_binary_rm, VEX_W; +} + +defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m, + int_x86_tbm_blcfill_u32, + int_x86_tbm_blcfill_u64>; +defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m, + int_x86_tbm_blci_u32, + int_x86_tbm_blci_u64>; +defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m, + int_x86_tbm_blcic_u32, + int_x86_tbm_blcic_u64>; +defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m, + int_x86_tbm_blcmsk_u32, + int_x86_tbm_blcmsk_u64>; +defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m, + int_x86_tbm_blcs_u32, + int_x86_tbm_blcs_u64>; +defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m, + int_x86_tbm_blsfill_u32, + int_x86_tbm_blsfill_u64>; +defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m, + int_x86_tbm_blsic_u32, + int_x86_tbm_blsic_u64>; +defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m, + int_x86_tbm_t1mskc_u32, + int_x86_tbm_t1mskc_u64>; +defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m, + int_x86_tbm_tzmsk_u32, + int_x86_tbm_tzmsk_u64>; +} // isAsmParserOnly, HasTBM, EFLAGS + //===----------------------------------------------------------------------===// // Subsystems. //===----------------------------------------------------------------------===// -- cgit v1.2.3