From b4bc424c9acd787fbfcd1506aadd6e49113f6b1c Mon Sep 17 00:00:00 2001 From: Mehdi Amini Date: Fri, 24 Jul 2015 01:44:39 +0000 Subject: Remove access to the DataLayout in the TargetMachine Summary: Replace getDataLayout() with a createDataLayout() method to make explicit that it is intended to create a DataLayout only and not accessing it for other purpose. This change is the last of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: jholewinski, llvm-commits, rafael, yaron.keren Differential Revision: http://reviews.llvm.org/D11103 (cherry picked from commit 5609fc56bca971e5a7efeaa6ca4676638eaec5ea) From: Mehdi Amini llvm-svn: 243083 --- llvm/lib/Target/Sparc/SparcISelLowering.cpp | 10 ++++----- llvm/lib/Target/SystemZ/SystemZISelLowering.cpp | 3 +-- llvm/lib/Target/TargetMachineC.cpp | 30 ++++++++++++++----------- llvm/lib/Target/X86/X86ISelLowering.cpp | 10 +++++---- 4 files changed, 29 insertions(+), 24 deletions(-) (limited to 'llvm/lib/Target') diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp index 4879d4ee79e..67918a7c319 100644 --- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -1370,7 +1370,7 @@ static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { SparcTargetLowering::SparcTargetLowering(TargetMachine &TM, const SparcSubtarget &STI) : TargetLowering(TM), Subtarget(&STI) { - auto &DL = *TM.getDataLayout(); + MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize()); // Set up the register classes. addRegisterClass(MVT::i32, &SP::IntRegsRegClass); @@ -1396,10 +1396,10 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM, setTruncStoreAction(MVT::f128, MVT::f64, Expand); // Custom legalize GlobalAddress nodes into LO/HI parts. - setOperationAction(ISD::GlobalAddress, getPointerTy(DL), Custom); - setOperationAction(ISD::GlobalTLSAddress, getPointerTy(DL), Custom); - setOperationAction(ISD::ConstantPool, getPointerTy(DL), Custom); - setOperationAction(ISD::BlockAddress, getPointerTy(DL), Custom); + setOperationAction(ISD::GlobalAddress, PtrVT, Custom); + setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom); + setOperationAction(ISD::ConstantPool, PtrVT, Custom); + setOperationAction(ISD::BlockAddress, PtrVT, Custom); // Sparc doesn't have sext_inreg, replace them with shl/sra setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index 056ee02dcc2..3c5d185ffe8 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -84,8 +84,7 @@ static MachineOperand earlyUseOperand(MachineOperand Op) { SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM, const SystemZSubtarget &STI) : TargetLowering(TM), Subtarget(STI) { - auto &DL = *TM.getDataLayout(); - MVT PtrVT = getPointerTy(DL); + MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize()); // Set up the register classes. if (Subtarget.hasHighWord()) diff --git a/llvm/lib/Target/TargetMachineC.cpp b/llvm/lib/Target/TargetMachineC.cpp index 719923558de..eae23e6e67f 100644 --- a/llvm/lib/Target/TargetMachineC.cpp +++ b/llvm/lib/Target/TargetMachineC.cpp @@ -32,15 +32,25 @@ using namespace llvm; + +// The TargetMachine uses to offer access to a DataLayout member. This is reflected +// in the C API. For backward compatibility reason, this structure allows to keep +// a DataLayout member accessible to C client that have a handle to a +// LLVMTargetMachineRef. +struct LLVMOpaqueTargetMachine { + std::unique_ptr Machine; + DataLayout DL; +}; + + inline TargetMachine *unwrap(LLVMTargetMachineRef P) { - return reinterpret_cast(P); + return P->Machine.get(); } inline Target *unwrap(LLVMTargetRef P) { return reinterpret_cast(P); } inline LLVMTargetMachineRef wrap(const TargetMachine *P) { - return - reinterpret_cast(const_cast(P)); + return new LLVMOpaqueTargetMachine{ std::unique_ptr(const_cast(P)), P->createDataLayout() }; } inline LLVMTargetRef wrap(const Target * P) { return reinterpret_cast(const_cast(P)); @@ -147,7 +157,7 @@ LLVMTargetMachineRef LLVMCreateTargetMachine(LLVMTargetRef T, void LLVMDisposeTargetMachine(LLVMTargetMachineRef T) { - delete unwrap(T); + delete T; } LLVMTargetRef LLVMGetTargetMachineTarget(LLVMTargetMachineRef T) { @@ -170,8 +180,9 @@ char* LLVMGetTargetMachineFeatureString(LLVMTargetMachineRef T) { return strdup(StringRep.c_str()); } +/// @deprecated: see "struct LLVMOpaqueTargetMachine" description above LLVMTargetDataRef LLVMGetTargetMachineData(LLVMTargetMachineRef T) { - return wrap(unwrap(T)->getDataLayout()); + return wrap(&T->DL); } void LLVMSetTargetMachineAsmVerbosity(LLVMTargetMachineRef T, @@ -190,14 +201,7 @@ static LLVMBool LLVMTargetMachineEmit(LLVMTargetMachineRef T, LLVMModuleRef M, std::string error; - const DataLayout *td = TM->getDataLayout(); - - if (!td) { - error = "No DataLayout in TargetMachine"; - *ErrorMessage = strdup(error.c_str()); - return true; - } - Mod->setDataLayout(*td); + Mod->setDataLayout(TM->createDataLayout()); TargetMachine::CodeGenFileType ft; switch (codegen) { diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 4c09eaf12c8..ff0daf9eb71 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -76,7 +76,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, : TargetLowering(TM), Subtarget(&STI) { X86ScalarSSEf64 = Subtarget->hasSSE2(); X86ScalarSSEf32 = Subtarget->hasSSE1(); - TD = TM.getDataLayout(); + MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize()); // Set up the TargetLowering object. static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; @@ -505,7 +505,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); - setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(*TD), Custom); + setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom); // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering. setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom); @@ -16515,9 +16515,11 @@ SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, for (FunctionType::param_iterator I = FTy->param_begin(), E = FTy->param_end(); I != E; ++I, ++Idx) - if (Attrs.hasAttribute(Idx, Attribute::InReg)) + if (Attrs.hasAttribute(Idx, Attribute::InReg)) { + auto &DL = DAG.getDataLayout(); // FIXME: should only count parameters that are lowered to integers. - InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; + InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32; + } if (InRegCount > 2) { report_fatal_error("Nest register in use - reduce number of inreg" -- cgit v1.2.3