From a8426b43f8b99217e564b21a9d7aef7871292b4c Mon Sep 17 00:00:00 2001 From: Pablo Barrio Date: Mon, 5 Aug 2019 17:38:58 +0000 Subject: [AArch64] Set preferred function alignment to 16 bytes on Neoverse N1 Summary: The Arm Neoverse N1 Software Optimization Guide [1], Section "4.8 Branch instruction alignment" states: "Consider aligning subroutine entry points and branch targets to 32B boundaries, within the bounds of the code-density requirements of the program." This patch sets the preferred function alignment on Neoverse N1 to 2^4=16B. This was already the case in some of the latest Cortex-A CPUs. Benchmarking in previous Cortex-A CPUs suggested that 16B alignment is already better than the default. See commit d04ee305. The reason we don't set it to 32B right now (as the optimisation guide suggests) is that this will impact code size and perhaps the instruction cache performance. Therefore we need benchmark numbers first. I have also added testing for A75 and A76 that we were missing. [1] https://developer.arm.com/docs/swog309707/latest Reviewers: fhahn, greened, samparker, dmgreen Reviewed By: dmgreen Subscribers: dmgreen, javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65654 llvm-svn: 367894 --- llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 2 ++ 1 file changed, 2 insertions(+) (limited to 'llvm/lib/Target') diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp index fb82b264706..9103287bf8c 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -125,7 +125,9 @@ void AArch64Subtarget::initializeProperties() { MinVectorRegisterBitWidth = 128; break; case NeoverseE1: + break; case NeoverseN1: + PrefFunctionAlignment = 4; break; case Saphira: MaxInterleaveFactor = 4; -- cgit v1.2.3