From 9faa09b21e15fdb548abc26cb561d0773fc19798 Mon Sep 17 00:00:00 2001 From: Diana Picus Date: Thu, 23 Nov 2017 12:44:20 +0000 Subject: [ARM GlobalISel] Support G_FMUL for s32 and s64 TableGen already generates code for selecting a G_FMUL, so we only need to add a test for that part. For the legalizer and reg bank select, we do the same thing as the other floating point binary operators: either mark as legal if we have a FP unit or lower to a libcall, and map to the floating point registers. llvm-svn: 318910 --- llvm/lib/Target/ARM/ARMLegalizerInfo.cpp | 4 ++-- llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) (limited to 'llvm/lib/Target') diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp index 357e5a13784..6db3ca76187 100644 --- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp +++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp @@ -148,7 +148,7 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) { setAction({G_ICMP, 1, Ty}, Legal); if (!ST.useSoftFloat() && ST.hasVFP2()) { - for (unsigned BinOp : {G_FADD, G_FSUB}) + for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL}) for (auto Ty : {s32, s64}) setAction({BinOp, Ty}, Legal); @@ -159,7 +159,7 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) { setAction({G_FCMP, 1, s32}, Legal); setAction({G_FCMP, 1, s64}, Legal); } else { - for (unsigned BinOp : {G_FADD, G_FSUB}) + for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL}) for (auto Ty : {s32, s64}) setAction({BinOp, Ty}, Libcall); diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp index 62bcc869d30..bcae1c93974 100644 --- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -243,7 +243,8 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { break; } case G_FADD: - case G_FSUB: { + case G_FSUB: + case G_FMUL: { LLT Ty = MRI.getType(MI.getOperand(0).getReg()); OperandsMapping =Ty.getSizeInBits() == 64 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] -- cgit v1.2.3