From 9d6347cfc19eaeb985fb445a5f8d00af4514f0da Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Wed, 6 Mar 2019 18:52:52 +0000
Subject: [DAGCombine] Improve select (not Cond), N1, N2 -> select Cond, N2, N1
 fold

Move the x86 combine from D58974 into the DAGCombine VSELECT code and update the SELECT version to use the isBooleanFlip helper as well.

Requested by @spatel on D59006

llvm-svn: 355533
---
 llvm/lib/Target/X86/X86ISelLowering.cpp | 6 ------
 1 file changed, 6 deletions(-)

(limited to 'llvm/lib/Target')

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index afb76014dff..fa18985e4f8 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -34684,12 +34684,6 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
       return DAG.getVectorShuffle(VT, DL, LHS, RHS, Mask);
   }
 
-  // Commute LHS/RHS if the Cond has been XOR'd.
-  // TODO: Move this to DAGCombine.
-  if (CondVT.getScalarSizeInBits() == VT.getScalarSizeInBits() &&
-      isBitwiseNot(Cond))
-    return DAG.getNode(N->getOpcode(), DL, VT, Cond.getOperand(0), RHS, LHS);
-
   // If we have SSE[12] support, try to form min/max nodes. SSE min/max
   // instructions match the semantics of the common C idiom x<y?x:y but not
   // x<=y?x:y, because of how they handle negative zero (which can be
-- 
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