From 91294c5bdcb745ab356b3dd255e2c2db1a91d50a Mon Sep 17 00:00:00 2001 From: Chad Rosier Date: Wed, 18 May 2016 17:43:11 +0000 Subject: [AArch64] Minor refactoring. NFC. llvm-svn: 269963 --- llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'llvm/lib/Target') diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index aa6477789c7..65a8769dae4 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -1987,13 +1987,12 @@ static bool tryBitfieldInsertOpFromOr(SDNode *N, const APInt &UsefulBits, SelectionDAG *CurDAG) { assert(N->getOpcode() == ISD::OR && "Expect a OR operation"); - SDValue Dst, Src; - unsigned ImmR, ImmS; - EVT VT = N->getValueType(0); if (VT != MVT::i32 && VT != MVT::i64) return false; + unsigned BitWidth = VT.getSizeInBits(); + // Because of simplify-demanded-bits in DAGCombine, involved masks may not // have the expected shape. Try to undo that. @@ -2011,6 +2010,8 @@ static bool tryBitfieldInsertOpFromOr(SDNode *N, const APInt &UsefulBits, // and/or inserting fewer extra instructions. for (int I = 0; I < 4; ++I) { + SDValue Dst, Src; + unsigned ImmR, ImmS; bool BiggerPattern = I / 2; SDNode *OrOpd0 = N->getOperand(I % 2).getNode(); SDValue OrOpd1Val = N->getOperand((I + 1) % 2); @@ -2040,7 +2041,7 @@ static bool tryBitfieldInsertOpFromOr(SDNode *N, const APInt &UsefulBits, } else if (isBitfieldPositioningOp(CurDAG, SDValue(OrOpd0, 0), BiggerPattern, Src, DstLSB, Width)) { - ImmR = (VT.getSizeInBits() - DstLSB) % VT.getSizeInBits(); + ImmR = (BitWidth - DstLSB) % BitWidth; ImmS = Width - 1; } else continue; -- cgit v1.2.3