From 8f5e0085342ce331da119ba38c48664a93080f78 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Sat, 21 May 2016 00:53:28 +0000 Subject: AMDGPU: Fix relationship between SReg_32 and SReg_32_XM0 llvm-svn: 270300 --- llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'llvm/lib/Target') diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td index 6c6fa3c5f9a..0c3dc2143cd 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td @@ -249,12 +249,6 @@ class RegImmMatcher : AsmOperandClass { let RenderMethod = "addRegOrImmOperands"; } -// Register class for all scalar registers (SGPRs + Special Registers) -def SReg_32 : RegisterClass<"AMDGPU", [i32, f32], 32, - (add SGPR_32, M0, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI, - TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI) ->; - // Subset of SReg_32 without M0 for SMRD instructions and alike. // See comments in SIInstructions.td for more info. def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32], 32, @@ -262,6 +256,11 @@ def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32], 32, TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI) >; +// Register class for all scalar registers (SGPRs + Special Registers) +def SReg_32 : RegisterClass<"AMDGPU", [i32, f32], 32, + (add SReg_32_XM0, M0) +>; + def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 32, (add SGPR_64Regs)>; def TTMP_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 32, (add TTMP_64Regs)> { -- cgit v1.2.3