From 62c7032c1832d50d474f562341a3283c5c6aa521 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Fri, 17 May 2019 14:04:56 +0000 Subject: [X86][AVX] isNOT - add extract_subvector(xor X, -1) -> extract_subvector(X) fold. Prep work for the removal of the remaining x86 CTTZ vector lowering. llvm-svn: 361035 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'llvm/lib/Target') diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index a63110070c4..6366f2e4f7c 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -37448,11 +37448,20 @@ static SDValue combineCompareEqual(SDNode *N, SelectionDAG &DAG, } // Match (xor X, -1) -> X. +// Match extract_subvector(xor X, -1) -> extract_subvector(X). static SDValue IsNOT(SDValue V, SelectionDAG &DAG) { V = peekThroughBitcasts(V); if (V.getOpcode() == ISD::XOR && ISD::isBuildVectorAllOnes(V.getOperand(1).getNode())) return V.getOperand(0); + if (V.getOpcode() == ISD::EXTRACT_SUBVECTOR && + (isNullConstant(V.getOperand(1)) || V.getOperand(0).hasOneUse())) { + if (SDValue Not = IsNOT(V.getOperand(0), DAG)) { + Not = DAG.getBitcast(V.getOperand(0).getValueType(), Not); + return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(Not), V.getValueType(), + Not, V.getOperand(1)); + } + } return SDValue(); } -- cgit v1.2.3