From 376113da89d0b32bfcbdfea6476ab441f4ef3537 Mon Sep 17 00:00:00 2001 From: Chandler Carruth Date: Tue, 24 Jul 2018 12:19:01 +0000 Subject: [x86/SLH] Tidy up a comment, using doxygen structure and wording it to be more accurate and understandable. llvm-svn: 337822 --- llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'llvm/lib/Target') diff --git a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp index c2453cef496..10e1132d877 100644 --- a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp +++ b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp @@ -1866,11 +1866,13 @@ bool X86SpeculativeLoadHardeningPass::canHardenRegister(unsigned Reg) { return RC->hasSuperClassEq(GPRRegClasses[Log2_32(RegBytes)]); } -// We can harden non-leaking loads into register without touching the address -// by just hiding all of the loaded bits. We use an `or` instruction to do -// this because having the poison value be all ones allows us to use the same -// value below. And the goal is just for the loaded bits to not be exposed to -// execution and coercing them to one is sufficient. +/// Harden a load by hardening the loaded value in the defined register. +/// +/// We can harden a non-leaking load into a register without touching the +/// address by just hiding all of the loaded bits during misspeculation. We use +/// an `or` instruction to do this because we set up our poison value as all +/// ones. And the goal is just for the loaded bits to not be exposed to +/// execution and coercing them to one is sufficient. void X86SpeculativeLoadHardeningPass::hardenPostLoad(MachineInstr &MI) { MachineBasicBlock &MBB = *MI.getParent(); DebugLoc Loc = MI.getDebugLoc(); -- cgit v1.2.3