From 31f482c26bc4452f4c41d90c73bb709d00cd0264 Mon Sep 17 00:00:00 2001 From: David Stuttard Date: Wed, 18 Apr 2018 13:53:31 +0000 Subject: [AMDGPU] Fix issues for backend divergence tracking Summary: A change to use divergence analysis in the AMDGPU backend was getting formal arguments incorrect (not tagged as divergent) unless they were VGPR0, VGPR1 or VGPR2 For graphics shaders it is possible to have more than these passed in as VGPR Modified the checking code to check for any VGPR registers passed in as formal arguments. Also, some intrinsics that are sources of divergence may have been lowered during instruction selection and are missed on subsequent calls to isSDNodeSourceOfDivergence - added the relevant AMDGPUISD checks as well. Finally, the FunctionLoweringInfo tracks virtual registers that are live across basic block boundaries. This is used to check for divergence of CopyFromRegister registers using the DivergenceAnalysis analysis. For multiple blocks the lazily evaluated inverted map VirtReg2Value was not cleared when the ValueMap map was. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D45372 Change-Id: I112f3bd6dfe0f62e63ce9b43b893982778e4bee3 llvm-svn: 330257 --- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'llvm/lib/Target') diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index f142ef6b01e..0ede62ba4d4 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -806,12 +806,11 @@ bool AMDGPUTargetLowering::isSDNodeSourceOfDivergence(const SDNode * N, if (MRI.isLiveIn(Reg)) { // workitem.id.x workitem.id.y workitem.id.z + // Any VGPR formal argument is also considered divergent if ((MRI.getLiveInPhysReg(Reg) == AMDGPU::T0_X) || (MRI.getLiveInPhysReg(Reg) == AMDGPU::T0_Y) || - (MRI.getLiveInPhysReg(Reg) == AMDGPU::T0_Z)|| - (MRI.getLiveInPhysReg(Reg) == AMDGPU::VGPR0) || - (MRI.getLiveInPhysReg(Reg) == AMDGPU::VGPR1) || - (MRI.getLiveInPhysReg(Reg) == AMDGPU::VGPR2)) + (MRI.getLiveInPhysReg(Reg) == AMDGPU::T0_Z) || + (TRI.isVGPR(MRI, Reg))) return true; // Formal arguments of non-entry functions // are conservatively considered divergent @@ -840,6 +839,12 @@ bool AMDGPUTargetLowering::isSDNodeSourceOfDivergence(const SDNode * N, case ISD::INTRINSIC_W_CHAIN: return AMDGPU::isIntrinsicSourceOfDivergence( cast(N->getOperand(1))->getZExtValue()); + // In some cases intrinsics that are a source of divergence have been + // lowered to AMDGPUISD so we also need to check those too. + case AMDGPUISD::INTERP_MOV: + case AMDGPUISD::INTERP_P1: + case AMDGPUISD::INTERP_P2: + return true; } return false; } -- cgit v1.2.3