From 0e5312787e81c837d1e2a2347145ea0b27c22bf8 Mon Sep 17 00:00:00 2001 From: Quentin Colombet Date: Tue, 11 Oct 2016 00:21:11 +0000 Subject: [AArch64][InstructionSelector] Teach the selector how to handle vector OR. This only adds the support for 64-bit vector OR. Adding more sizes is not difficult, but it requires a bigger refactoring because ORs work on any size, not necessarly the ones that match the width of the register width. Right now, this is not expressed in the legalization, so don't bother pushing the refactoring yet. llvm-svn: 283831 --- llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp | 2 ++ 1 file changed, 2 insertions(+) (limited to 'llvm/lib/Target') diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index b534f248e40..c8a00199e27 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -175,6 +175,8 @@ static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, return AArch64::FMULDrr; case TargetOpcode::G_FDIV: return AArch64::FDIVDrr; + case TargetOpcode::G_OR: + return AArch64::ORRv8i8; default: return GenericOpc; } -- cgit v1.2.3