From dfa9dbceaaffae755963e47ceb90a8d681dd8bc9 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Tue, 24 Aug 2004 08:18:44 +0000 Subject: Add -sse[,2,3] arguments to LLC llvm-svn: 16018 --- llvm/lib/Target/X86/X86TargetMachine.cpp | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'llvm/lib/Target/X86/X86TargetMachine.cpp') diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp index 51ba378135d..1a9e978dc4a 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.cpp +++ b/llvm/lib/Target/X86/X86TargetMachine.cpp @@ -25,6 +25,8 @@ #include "Support/Statistic.h" using namespace llvm; +X86VectorEnum llvm::X86Vector = NoSSE; + namespace { cl::opt NoSSAPeephole("disable-ssa-peephole", cl::init(true), cl::desc("Disable the ssa-based peephole optimizer " @@ -33,6 +35,18 @@ namespace { cl::desc("Disable the X86 asm printer, for use " "when profiling the code generator.")); + // FIXME: This should eventually be handled with target triples and + // subtarget support! + cl::opt + SSEArg( + cl::desc("Enable SSE support in the X86 target:"), + cl::values( + clEnumValN(SSE, "sse", " Enable SSE support"), + clEnumValN(SSE2, "sse2", " Enable SSE and SSE2 support"), + clEnumValN(SSE3, "sse3", " Enable SSE, SSE2, and SSE3 support"), + clEnumValEnd), + cl::location(X86Vector), cl::init(NoSSE)); + // Register the target. RegisterTarget X("x86", " IA-32 (Pentium and above)"); } -- cgit v1.2.3