From 48ca0550ddccc3a9c46ab11600cf77688cbdb62c Mon Sep 17 00:00:00 2001 From: Alexander Ivchenko Date: Tue, 10 Jul 2018 16:38:35 +0000 Subject: [GlobalISel][X86_64] Support for G_SITOFP The instruction selection is automatically handled by tablegen llvm-svn: 336703 --- llvm/lib/Target/X86/X86RegisterBankInfo.cpp | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'llvm/lib/Target/X86/X86RegisterBankInfo.cpp') diff --git a/llvm/lib/Target/X86/X86RegisterBankInfo.cpp b/llvm/lib/Target/X86/X86RegisterBankInfo.cpp index 85d230e4b20..246d6d5a58d 100644 --- a/llvm/lib/Target/X86/X86RegisterBankInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterBankInfo.cpp @@ -198,6 +198,17 @@ X86RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { // Instruction having only floating-point operands (all scalars in VECRReg) getInstrPartialMappingIdxs(MI, MRI, /* isFP */ true, OpRegBankIdx); break; + case TargetOpcode::G_SITOFP: { + // Some of the floating-point instructions have mixed GPR and FP operands: + // fine-tune the computed mapping. + auto &Op0 = MI.getOperand(0); + auto &Op1 = MI.getOperand(1); + const LLT Ty0 = MRI.getType(Op0.getReg()); + const LLT Ty1 = MRI.getType(Op1.getReg()); + OpRegBankIdx[0] = getPartialMappingIdx(Ty0, /* isFP */ true); + OpRegBankIdx[1] = getPartialMappingIdx(Ty1, /* isFP */ false); + break; + } case TargetOpcode::G_TRUNC: case TargetOpcode::G_ANYEXT: { auto &Op0 = MI.getOperand(0); -- cgit v1.2.3