From 58827ff98ed3f391ea629602795dca9caea990b6 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Fri, 5 Feb 2010 22:10:22 +0000 Subject: port X86InstrInfo::determineREX over to the new encoder. llvm-svn: 95440 --- llvm/lib/Target/X86/X86InstrInfo.cpp | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'llvm/lib/Target/X86/X86InstrInfo.cpp') diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index f60432de318..d420aa71b9f 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -3015,11 +3015,10 @@ isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { } -/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register? -/// e.g. r8, xmm8, etc. -bool X86InstrInfo::isX86_64ExtendedReg(const MachineOperand &MO) { - if (!MO.isReg()) return false; - switch (MO.getReg()) { +/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) +/// register? e.g. r8, xmm8, xmm13, etc. +bool X86InstrInfo::isX86_64ExtendedReg(unsigned RegNo) { + switch (RegNo) { default: break; case X86::R8: case X86::R9: case X86::R10: case X86::R11: case X86::R12: case X86::R13: case X86::R14: case X86::R15: -- cgit v1.2.3