From d3829c89bc29b17309ccb01f5ccc9eb34caf857f Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Sat, 22 Oct 2016 20:15:39 +0000 Subject: [X86][AVX512VL] Added support for combining target 256-bit shuffles to AVX512VL VPERMV3 llvm-svn: 284922 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 3 +++ 1 file changed, 3 insertions(+) (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp') diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 1431db77d78..3ffebf84521 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -25564,6 +25564,9 @@ static bool combineX86ShuffleChain(ArrayRef Inputs, SDValue Root, ((Subtarget.hasAVX512() && (MaskVT == MVT::v8f64 || MaskVT == MVT::v8i64 || MaskVT == MVT::v16f32 || MaskVT == MVT::v16i32)) || + (Subtarget.hasVLX() && + (MaskVT == MVT::v4f64 || MaskVT == MVT::v4i64 || + MaskVT == MVT::v8f32 || MaskVT == MVT::v8i32)) || (Subtarget.hasBWI() && MaskVT == MVT::v32i16) || (Subtarget.hasBWI() && Subtarget.hasVLX() && MaskVT == MVT::v16i16))) { MVT VPermMaskSVT = MVT::getIntegerVT(MaskEltSizeInBits); -- cgit v1.2.3