From a577bc26b6141673b1bf4a339953ab2c04b34a8d Mon Sep 17 00:00:00 2001 From: Chandler Carruth Date: Thu, 25 Sep 2014 01:13:38 +0000 Subject: [x86] Fix the v16i16 blend logic I added in the prior commit and add the missing test cases for it. Unsurprisingly, without test cases, there were bugs here. Surprisingly, this bug wasn't caught at compile time. Yep, there is an X86ISD::BLENDV. It isn't wired to anything. Oops. I'll fix than next. llvm-svn: 218434 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp') diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 9be0f23597a..0410b0761b7 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -7389,9 +7389,11 @@ static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1, V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1); V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2); - return DAG.getNode(ISD::BITCAST, DL, VT, DAG.getNode( - X86ISD::BLENDV, DL, MVT::v32i8, V1, V2, - DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PBLENDVMask))); + return DAG.getNode( + ISD::BITCAST, DL, VT, + DAG.getNode(ISD::VSELECT, DL, MVT::v32i8, + DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PBLENDVMask), + V1, V2)); } default: -- cgit v1.2.3