From 7ad77dfc2add2ccfe65318a984ee17435bc02a3c Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Wed, 22 Feb 2006 00:56:39 +0000
Subject: split register class handling from explicit physreg handling.

llvm-svn: 26308
---
 llvm/lib/Target/X86/X86ISelLowering.cpp | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

(limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index bbf590b8ac3..e32cc0f2bd8 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -1961,8 +1961,8 @@ void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
 }
 
 std::vector<unsigned> X86TargetLowering::
-getRegForInlineAsmConstraint(const std::string &Constraint,
-                             MVT::ValueType VT) const {
+getRegClassForInlineAsmConstraint(const std::string &Constraint,
+                                  MVT::ValueType VT) const {
   if (Constraint.size() == 1) {
     // FIXME: not handling fp-stack yet!
     // FIXME: not handling MMX registers yet ('y' constraint).
@@ -1993,6 +1993,5 @@ getRegForInlineAsmConstraint(const std::string &Constraint,
     }
   }
   
-  // Handle explicit register names.
-  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
+  return std::vector<unsigned>();
 }
-- 
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