From 61e628591f21c6d6e8ae11f1debf9c67fdadc48a Mon Sep 17 00:00:00 2001 From: Igor Breger Date: Tue, 7 Jun 2016 13:08:45 +0000 Subject: [AVX512] Fix load opcode for fast isel. Differential Revision: http://reviews.llvm.org/D21067 llvm-svn: 272006 --- llvm/lib/Target/X86/X86FastISel.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'llvm/lib/Target/X86/X86FastISel.cpp') diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp index d06d7e22d49..d62a3c7a78b 100644 --- a/llvm/lib/Target/X86/X86FastISel.cpp +++ b/llvm/lib/Target/X86/X86FastISel.cpp @@ -452,7 +452,7 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM, assert(Subtarget->hasAVX512()); // Note: There are a lot more choices based on type with AVX-512, but // there's really no advantage when the load isn't masked. - Opc = (Alignment >= 64) ? X86::VMOVDQA64Zmr : X86::VMOVDQU64Zmr; + Opc = (Alignment >= 64) ? X86::VMOVDQA64Zrm : X86::VMOVDQU64Zrm; RC = &X86::VR512RegClass; break; } -- cgit v1.2.3