From 35fd79237f19866c56355984f358b6f0115c213b Mon Sep 17 00:00:00 2001 From: Kevin Enderby Date: Thu, 20 Jun 2013 22:32:18 +0000 Subject: Update the X86 disassembler to use xacquire and xrelease when appropriate. This is a bit tricky as the xacquire and xrelease hints use the same bytes, 0xf2 and 0xf3, as the repne and rep prefixes. Fortunately llvm has different llvm MCInst Opcode enums for rep/xrelease and repne/xacquire. So to make this work a boolean was added the InternalInstruction struct as part of the Prefix state which is set with the added logic in readPrefixes() when decoding an instruction to determine if these prefix bytes are to be disassembled as xacquire or xrelease. Then we let the matcher pick the normal prefix instructionID and we change the Opcode after that when it is set into the MCInst being created. rdar://11019859 llvm-svn: 184490 --- llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp') diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp index ca71c4f3519..f03068e0cdc 100644 --- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -683,6 +683,15 @@ static bool translateInstruction(MCInst &mcInst, } mcInst.setOpcode(insn.instructionID); + // If when reading the prefix bytes we determined the overlapping 0xf2 or 0xf3 + // prefix bytes should be disassembled as xrelease and xacquire then set the + // opcode to those instead of the rep and repne opcodes. + if (insn.xAcquireRelease) { + if(mcInst.getOpcode() == X86::REP_PREFIX) + mcInst.setOpcode(X86::XRELEASE_PREFIX); + else if(mcInst.getOpcode() == X86::REPNE_PREFIX) + mcInst.setOpcode(X86::XACQUIRE_PREFIX); + } int index; -- cgit v1.2.3