From aaf4e2cbbabfe8f97925665b49d885aa0e5b703a Mon Sep 17 00:00:00 2001
From: Thomas Lively <tlively@google.com>
Date: Tue, 18 Sep 2018 21:45:12 +0000
Subject: [WebAssembly] v4f32.abs and v2f64.abs

Summary: implement lowering of @llvm.fabs for vector types.

Reviewers: aheejin, dschuff

Subscribers:

llvm-svn: 342513
---
 llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'llvm/lib/Target/WebAssembly')

diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
index 51333181559..973a0787da7 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -207,6 +207,11 @@ multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> {
   defm "" : SIMDCondition<v2f64, v2i64, "f64x2", name, cond,
                               !add(baseInst, 1)>;
 }
+multiclass SIMDAbs<ValueType vec_t, string vec, bits<32> simdop> {
+  defm ABS_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
+                           [(set (vec_t V128:$dst), (vec_t (fabs V128:$vec)))],
+                           vec#".abs\t$dst, $vec", vec#".abs", simdop>;
+}
 
 let Defs = [ARGUMENTS] in {
 defm "" : ConstVec<v16i8,
@@ -363,6 +368,9 @@ defm GE_S : SIMDConditionInt<"ge_s", SETGE, 106, 2>;
 defm GE_U : SIMDConditionInt<"ge_u", SETUGE, 107, 2>;
 defm GE : SIMDConditionFP<"ge", SETOGE, 112>;
 
+defm "" : SIMDAbs<v4f32, "f32x4", 116>;
+defm "" : SIMDAbs<v2f64, "f64x2", 117>;
+
 } // Defs = [ARGUMENTS]
 
 // Def load and store patterns from WebAssemblyInstrMemory.td for vector types
-- 
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