From def708a0f9ff4331214fded128fa2d5d6459952c Mon Sep 17 00:00:00 2001 From: Zhan Jun Liau Date: Mon, 11 Jul 2016 18:45:03 +0000 Subject: [SystemZ] Recognize Load On Condition Immediate (LOCHI/LOGHI) opportunities Summary: Add support for the z13 instructions LOCHI and LOCGHI which conditionally load immediate values. Add target instruction info hooks so that if conversion will allow predication of LHI/LGHI. Author: RolandF Reviewers: uweigand Subscribers: zhanjunl Commiting on behalf of Roland. Differential Revision: http://reviews.llvm.org/D22117 llvm-svn: 275086 --- llvm/lib/Target/SystemZ/SystemZInstrFormats.td | 30 ++++++++++++++++++++++++++ llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 20 +++++++++++++++++ llvm/lib/Target/SystemZ/SystemZInstrInfo.td | 12 +++++++++++ llvm/lib/Target/SystemZ/SystemZProcessors.td | 7 +++++- llvm/lib/Target/SystemZ/SystemZSubtarget.cpp | 2 +- llvm/lib/Target/SystemZ/SystemZSubtarget.h | 4 ++++ 6 files changed, 73 insertions(+), 2 deletions(-) (limited to 'llvm/lib/Target/SystemZ') diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td index 91181dee04c..973894d5c00 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td @@ -1308,6 +1308,15 @@ class CondUnaryRRF opcode, RegisterOperand cls1, let R4 = 0; } +class CondUnaryRIE opcode, RegisterOperand cls, + Immediate imm> + : InstRIEd, + Requires<[FeatureLoadStoreOnCond2]> { + let CCMaskLast = 1; +} + // Like CondUnaryRRF, but used for the raw assembly form. The condition-code // mask is the third operand rather than being part of the mnemonic. class AsmCondUnaryRRF opcode, RegisterOperand cls1, @@ -1320,6 +1329,16 @@ class AsmCondUnaryRRF opcode, RegisterOperand cls1, let R4 = 0; } +class AsmCondUnaryRIE opcode, RegisterOperand cls, + Immediate imm> + : InstRIEd, + Requires<[FeatureLoadStoreOnCond2]> { + let Constraints = "$R1 = $R1src"; + let DisableEncoding = "$R1src"; +} + // Like CondUnaryRRF, but with a fixed CC mask. class FixedCondUnaryRRF opcode, RegisterOperand cls1, RegisterOperand cls2, bits<4> ccmask> @@ -1332,6 +1351,17 @@ class FixedCondUnaryRRF opcode, RegisterOperand cls1, let R4 = 0; } +class FixedCondUnaryRIE opcode, RegisterOperand cls, + Immediate imm, bits<4> ccmask> + : InstRIEd, + Requires<[FeatureLoadStoreOnCond2]> { + let Constraints = "$R1 = $R1src"; + let DisableEncoding = "$R1src"; + let R3 = ccmask; +} + class UnaryRI opcode, SDPatternOperator operator, RegisterOperand cls, Immediate imm> : InstRIgetParent(), MI) + .addImm(CCValid) + .addImm(CCMask) + .addReg(SystemZ::CC, RegState::Implicit); + return true; + } + } if (Opcode == SystemZ::Trap) { MI.setDesc(get(SystemZ::CondTrap)); MachineInstrBuilder(*MI.getParent()->getParent(), MI) diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td index 6f77873872b..c510ca774be 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td @@ -205,6 +205,10 @@ multiclass CondExtendedMnemonicA ccmask, string name> { } def LOCR : FixedCondUnaryRRF<"locr"##name, 0xB9F2, GR32, GR32, ccmask>; def LOCGR : FixedCondUnaryRRF<"locgr"##name, 0xB9E2, GR64, GR64, ccmask>; + def LOCHI : FixedCondUnaryRIE<"lochi"##name, 0xEC42, GR64, imm32sx16, + ccmask>; + def LOCGHI: FixedCondUnaryRIE<"locghi"##name, 0xEC46, GR64, imm64sx16, + ccmask>; def LOC : FixedCondUnaryRSY<"loc"##name, 0xEBF2, GR32, ccmask, 4>; def LOCG : FixedCondUnaryRSY<"locg"##name, 0xEBE2, GR64, ccmask, 8>; def STOC : FixedCondStoreRSY<"stoc"##name, 0xEBF3, GR32, ccmask, 4>; @@ -450,6 +454,14 @@ let Uses = [CC] in { def AsmLOCR : AsmCondUnaryRRF<"loc", 0xB9F2, GR32, GR32>; def AsmLOCGR : AsmCondUnaryRRF<"locg", 0xB9E2, GR64, GR64>; } +let isCodeGenOnly = 1, Uses = [CC] in { + def LOCHI : CondUnaryRIE<"lochi", 0xEC42, GR32, imm32sx16>; + def LOCGHI : CondUnaryRIE<"locghi", 0xEC46, GR64, imm64sx16>; +} +let Uses = [CC] in { + def AsmLOCHI : AsmCondUnaryRIE<"lochi", 0xEC42, GR32, imm32sx16>; + def AsmLOCGHI : AsmCondUnaryRIE<"locghi", 0xEC46, GR64, imm64sx16>; +} // Immediate moves. let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1, diff --git a/llvm/lib/Target/SystemZ/SystemZProcessors.td b/llvm/lib/Target/SystemZ/SystemZProcessors.td index 01773eeed5a..9adc0189e65 100644 --- a/llvm/lib/Target/SystemZ/SystemZProcessors.td +++ b/llvm/lib/Target/SystemZ/SystemZProcessors.td @@ -29,6 +29,11 @@ def FeatureLoadStoreOnCond : SystemZFeature< "Assume that the load/store-on-condition facility is installed" >; +def FeatureLoadStoreOnCond2 : SystemZFeature< + "load-store-on-cond-2", "LoadStoreOnCond2", + "Assume that the load/store-on-condition facility 2 is installed" +>; + def FeatureHighWord : SystemZFeature< "high-word", "HighWord", "Assume that the high-word facility is installed" @@ -94,4 +99,4 @@ def : Processor<"z13", NoItineraries, FeatureFastSerialization, FeatureInterlockedAccess1, FeatureMiscellaneousExtensions, FeatureTransactionalExecution, FeatureProcessorAssist, - FeatureVector]>; + FeatureVector, FeatureLoadStoreOnCond2]>; diff --git a/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp b/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp index 5fea9304f3f..67d5e0179fe 100644 --- a/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp +++ b/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp @@ -40,7 +40,7 @@ SystemZSubtarget::SystemZSubtarget(const Triple &TT, const std::string &CPU, HasPopulationCount(false), HasFastSerialization(false), HasInterlockedAccess1(false), HasMiscellaneousExtensions(false), HasTransactionalExecution(false), HasProcessorAssist(false), - HasVector(false), TargetTriple(TT), + HasVector(false), HasLoadStoreOnCond2(false), TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), TSInfo(), FrameLowering() {} diff --git a/llvm/lib/Target/SystemZ/SystemZSubtarget.h b/llvm/lib/Target/SystemZ/SystemZSubtarget.h index d091625f1b0..6007f6fc9c4 100644 --- a/llvm/lib/Target/SystemZ/SystemZSubtarget.h +++ b/llvm/lib/Target/SystemZ/SystemZSubtarget.h @@ -45,6 +45,7 @@ protected: bool HasTransactionalExecution; bool HasProcessorAssist; bool HasVector; + bool HasLoadStoreOnCond2; private: Triple TargetTriple; @@ -85,6 +86,9 @@ public: // Return true if the target has the load/store-on-condition facility. bool hasLoadStoreOnCond() const { return HasLoadStoreOnCond; } + // Return true if the target has the load/store-on-condition facility 2. + bool hasLoadStoreOnCond2() const { return HasLoadStoreOnCond2; } + // Return true if the target has the high-word facility. bool hasHighWord() const { return HasHighWord; } -- cgit v1.2.3