From 21235a256f0729722c972f6715dca3fc03f67d97 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Tue, 1 Oct 2013 12:49:07 +0000 Subject: [SystemZ] Add register zero extensions involving at least one high word llvm-svn: 191746 --- llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp') diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp index 199299379cf..ede1eceb8c0 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -102,6 +102,17 @@ void SystemZInstrInfo::expandRXYPseudo(MachineInstr *MI, unsigned LowOpcode, MI->setDesc(get(Opcode)); } +// MI is an RR-style pseudo instruction that zero-extends the low Size bits +// of one GRX32 into another. Replace it with LowOpcode if both operands +// are low registers, otherwise use RISB[LH]G. +void SystemZInstrInfo::expandZExtPseudo(MachineInstr *MI, unsigned LowOpcode, + unsigned Size) const { + emitGRX32Move(*MI->getParent(), MI, MI->getDebugLoc(), + MI->getOperand(0).getReg(), MI->getOperand(1).getReg(), + LowOpcode, Size, MI->getOperand(1).isKill()); + MI->eraseFromParent(); +} + // Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR // DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg // are low registers, otherwise use RISB[LH]G. Size is the number of bits @@ -814,6 +825,14 @@ SystemZInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH); return true; + case SystemZ::LLCRMux: + expandZExtPseudo(MI, SystemZ::LLCR, 8); + return true; + + case SystemZ::LLHRMux: + expandZExtPseudo(MI, SystemZ::LLHR, 16); + return true; + case SystemZ::LLCMux: expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH); return true; -- cgit v1.2.3