From 843d6933a00ab8081d98c0e38674be346e21831e Mon Sep 17 00:00:00 2001
From: Misha Brukman <brukman+llvm@gmail.com>
Date: Mon, 2 Jun 2003 20:55:14 +0000
Subject: SparcInstr.def: added 'r' and 'i' versions of MOV(F)cc instructions

SparcInstrSelection.cpp:
* Fixed opcodes to return correct 'i' version since the two functions are each
  only used in one place.
* Changed name of function to have an 'i' in the name to signify that they each
  return an immediate form of the opcode.
* Added a warning if either of the functions is ever used in a context which
  requires a register-version opcode.

SparcV9_F4.td: fixed class F4_3, added F4_4 and notes that F4_{1,2} need fixing
SparcV9.td: added the MOV(F)cc instructions

llvm-svn: 6548
---
 llvm/lib/Target/Sparc/SparcInstrSelection.cpp | 46 +++++++++++++++++----------
 1 file changed, 30 insertions(+), 16 deletions(-)

(limited to 'llvm/lib/Target/Sparc/SparcInstrSelection.cpp')

diff --git a/llvm/lib/Target/Sparc/SparcInstrSelection.cpp b/llvm/lib/Target/Sparc/SparcInstrSelection.cpp
index 93e121a9c4c..38a6c1652f3 100644
--- a/llvm/lib/Target/Sparc/SparcInstrSelection.cpp
+++ b/llvm/lib/Target/Sparc/SparcInstrSelection.cpp
@@ -402,19 +402,26 @@ ChooseBccInstruction(const InstructionNode* instrNode,
 }
 
 
+// WARNING: since this function has only one caller, it always returns
+// the opcode that expects an immediate and a register. If this function
+// is ever used in cases where an opcode that takes two registers is required,
+// then modify this function and use convertOpcodeFromRegToImm() where required.
+//
+// It will be necessary to expand convertOpcodeFromRegToImm() to handle the
+// new cases of opcodes.
 static inline MachineOpCode 
-ChooseMovFpccInstruction(const InstructionNode* instrNode)
+ChooseMovFpcciInstruction(const InstructionNode* instrNode)
 {
   MachineOpCode opCode = V9::INVALID_OPCODE;
   
   switch(instrNode->getInstruction()->getOpcode())
   {
-  case Instruction::SetEQ: opCode = V9::MOVFE;  break;
-  case Instruction::SetNE: opCode = V9::MOVFNE; break;
-  case Instruction::SetLE: opCode = V9::MOVFLE; break;
-  case Instruction::SetGE: opCode = V9::MOVFGE; break;
-  case Instruction::SetLT: opCode = V9::MOVFL;  break;
-  case Instruction::SetGT: opCode = V9::MOVFG;  break;
+  case Instruction::SetEQ: opCode = V9::MOVFEi;  break;
+  case Instruction::SetNE: opCode = V9::MOVFNEi; break;
+  case Instruction::SetLE: opCode = V9::MOVFLEi; break;
+  case Instruction::SetGE: opCode = V9::MOVFGEi; break;
+  case Instruction::SetLT: opCode = V9::MOVFLi;  break;
+  case Instruction::SetGT: opCode = V9::MOVFGi;  break;
   default:
     assert(0 && "Unrecognized VM instruction!");
     break; 
@@ -432,19 +439,26 @@ ChooseMovFpccInstruction(const InstructionNode* instrNode)
 //                      (i.e., we want to test inverse of a condition)
 // (The latter two cases do not seem to arise because SetNE needs nothing.)
 // 
+// WARNING: since this function has only one caller, it always returns
+// the opcode that expects an immediate and a register. If this function
+// is ever used in cases where an opcode that takes two registers is required,
+// then modify this function and use convertOpcodeFromRegToImm() where required.
+//
+// It will be necessary to expand convertOpcodeFromRegToImm() to handle the
+// new cases of opcodes.
 static MachineOpCode
-ChooseMovpccAfterSub(const InstructionNode* instrNode)
+ChooseMovpcciAfterSub(const InstructionNode* instrNode)
 {
   MachineOpCode opCode = V9::INVALID_OPCODE;
   
   switch(instrNode->getInstruction()->getOpcode())
   {
-  case Instruction::SetEQ: opCode = V9::MOVE;  break;
-  case Instruction::SetLE: opCode = V9::MOVLE; break;
-  case Instruction::SetGE: opCode = V9::MOVGE; break;
-  case Instruction::SetLT: opCode = V9::MOVL;  break;
-  case Instruction::SetGT: opCode = V9::MOVG;  break;
-  case Instruction::SetNE: opCode = V9::MOVNE; break;
+  case Instruction::SetEQ: opCode = V9::MOVEi;  break;
+  case Instruction::SetLE: opCode = V9::MOVLEi; break;
+  case Instruction::SetGE: opCode = V9::MOVGEi; break;
+  case Instruction::SetLT: opCode = V9::MOVLi;  break;
+  case Instruction::SetGT: opCode = V9::MOVGi;  break;
+  case Instruction::SetNE: opCode = V9::MOVNEi; break;
   default: assert(0 && "Unrecognized VM instr!"); break; 
   }
   
@@ -2049,8 +2063,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
         
         if (computeBoolVal) {
           MachineOpCode movOpCode = (isFPCompare
-                                     ? ChooseMovFpccInstruction(subtreeRoot)
-                                     : ChooseMovpccAfterSub(subtreeRoot));
+                                     ? ChooseMovFpcciInstruction(subtreeRoot)
+                                     : ChooseMovpcciAfterSub(subtreeRoot));
 
           // Unconditionally set register to 0
           M = BuildMI(V9::SETHI, 2).addZImm(0).addRegDef(setCCInstr);
-- 
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