From 9b65ffb0976c5b9590959a6439d338fc5ec0dceb Mon Sep 17 00:00:00 2001 From: Sameer AbuAsal Date: Wed, 27 Jun 2018 20:51:42 +0000 Subject: [RISCV] Add machine function pass to merge base + offset Summary: In r333455 we added a peephole to fix the corner cases that result from separating base + offset lowering of global address.The peephole didn't handle some of the cases because it only has a basic block view instead of a function level view. This patch replaces that logic with a machine function pass. In addition to handling the original cases it handles uses of the global address across blocks in function and folding an offset from LW\SW instruction. This pass won't run for OptNone compilation, so there will be a negative impact overall vs the old approach at O0. Reviewers: asb, apazos, mgrang Reviewed By: asb Subscribers: MartinMosbeck, brucehoult, the_o, rogfer01, mgorny, rbar, johnrusso, simoncook, niosHD, kito-cheng, shiva0217, zzheng, llvm-commits, edward-jones Differential Revision: https://reviews.llvm.org/D47857 llvm-svn: 335786 --- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'llvm/lib/Target/RISCV/RISCVTargetMachine.cpp') diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index 29f6bead42f..a2ebf5bf3e6 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -78,6 +78,7 @@ public: void addIRPasses() override; bool addInstSelector() override; void addPreEmitPass() override; + void addPreRegAlloc() override; }; } @@ -97,3 +98,7 @@ bool RISCVPassConfig::addInstSelector() { } void RISCVPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); } + +void RISCVPassConfig::addPreRegAlloc() { + addPass(createRISCVMergeBaseOffsetOptPass()); +} -- cgit v1.2.3