From c3bf3d14ea66767e688242c93cb9920ad80b64a3 Mon Sep 17 00:00:00 2001 From: Luis Marques Date: Wed, 21 Aug 2019 14:00:58 +0000 Subject: [RISCV] Add support for RVC HINT instructions The hint instructions are enabled by default (if the standard C extension is enabled). To disable them pass -mattr=-rvc-hints. Differential Revision: https://reviews.llvm.org/D62592 llvm-svn: 369528 --- llvm/lib/Target/RISCV/RISCVSubtarget.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'llvm/lib/Target/RISCV/RISCVSubtarget.h') diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h index 12ba5f844b0..fa19252f1f1 100644 --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -42,6 +42,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { bool HasRV64 = false; bool IsRV32E = false; bool EnableLinkerRelax = false; + bool EnableRVCHintInstrs = false; unsigned XLen = 32; MVT XLenVT = MVT::i32; RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown; @@ -87,6 +88,7 @@ public: bool is64Bit() const { return HasRV64; } bool isRV32E() const { return IsRV32E; } bool enableLinkerRelax() const { return EnableLinkerRelax; } + bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; } MVT getXLenVT() const { return XLenVT; } unsigned getXLen() const { return XLen; } RISCVABI::ABI getTargetABI() const { return TargetABI; } -- cgit v1.2.3