From d834d8301d7d2219f4c6c29e7e0906d18a52fbe3 Mon Sep 17 00:00:00 2001 From: Alex Bradbury Date: Thu, 31 Jan 2019 22:48:38 +0000 Subject: [RISCV] Add RV64F codegen support This requires a little extra work due tothe fact i32 is not a legal type. When call lowering happens post-legalisation (e.g. when an intrinsic was inserted during legalisation). A bitcast from f32 to i32 can't be introduced. This is similar to the challenges with RV32D. To handle this, we introduce target-specific DAG nodes that perform bitcast+anyext for f32->i64 and trunc+bitcast for i64->f32. Differential Revision: https://reviews.llvm.org/D53235 llvm-svn: 352807 --- llvm/lib/Target/RISCV/RISCVISelLowering.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'llvm/lib/Target/RISCV/RISCVISelLowering.h') diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index fa18f7c8e40..12b63208543 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -41,7 +41,14 @@ enum NodeType : unsigned { // at instruction selection time. DIVW, DIVUW, - REMUW + REMUW, + // FPR32<->GPR transfer operations for RV64. Needed as an i32<->f32 bitcast + // is not legal on RV64. FMV_W_X_RV64 matches the semantics of the FMV.W.X. + // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result. + // This is a more convenient semantic for producing dagcombines that remove + // unnecessary GPR->FPR->GPR moves. + FMV_W_X_RV64, + FMV_X_ANYEXTW_RV64 }; } -- cgit v1.2.3