From 485defe58c3587c3520da5239363d24aa51f64c8 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 5 Nov 2014 19:01:17 +0000 Subject: R600/SI: Remove SI_ADDR64_RSRC llvm-svn: 221382 --- llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) (limited to 'llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp') diff --git a/llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp index 8a9340289d8..face98fe148 100644 --- a/llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp @@ -850,11 +850,6 @@ bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base, return true; } -static SDValue wrapAddr64Rsrc(SelectionDAG *DAG, SDLoc DL, SDValue Ptr) { - return SDValue(DAG->getMachineNode(AMDGPU::SI_ADDR64_RSRC, DL, MVT::v4i32, - Ptr), 0); -} - static bool isLegalMUBUFImmOffset(const ConstantSDNode *Imm) { return isUInt<12>(Imm->getZExtValue()); } @@ -930,9 +925,14 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, ConstantSDNode *C = cast(Addr64); if (C->getSExtValue()) { SDLoc DL(Addr); - SRsrc = wrapAddr64Rsrc(CurDAG, DL, Ptr); + + const SITargetLowering& Lowering = + *static_cast(getTargetLowering()); + + SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0); return true; } + return false; } @@ -951,7 +951,6 @@ static SDValue buildSMovImm32(SelectionDAG *DAG, SDLoc DL, uint64_t Val) { static SDValue buildRSRC(SelectionDAG *DAG, SDLoc DL, SDValue Ptr, uint32_t RsrcDword1, uint64_t RsrcDword2And3) { - SDValue PtrLo = DAG->getTargetExtractSubreg(AMDGPU::sub0, DL, MVT::i32, Ptr); SDValue PtrHi = DAG->getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr); if (RsrcDword1) { -- cgit v1.2.3