From 0cfb612413f48f1e0d394b96ef5ac2c127a150c1 Mon Sep 17 00:00:00 2001 From: Marcin Koscielnicki Date: Tue, 26 Apr 2016 10:37:22 +0000 Subject: [PowerPC] Add support for llvm.thread.pointer Differential Revision: http://reviews.llvm.org/D19304 llvm-svn: 267546 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'llvm/lib/Target/PowerPC') diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 72335a4f999..15efeb8cc9d 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -7715,6 +7715,16 @@ static bool getVectorCompareInfo(SDValue Intrin, int &CompareOpc, /// lower, do it, otherwise return null. SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { + unsigned IntrinsicID = + cast(Op.getOperand(0))->getZExtValue(); + + if (IntrinsicID == Intrinsic::thread_pointer) { + // Reads the thread pointer register, used for __builtin_thread_pointer. + bool is64bit = Subtarget.isPPC64(); + return DAG.getRegister(is64bit ? PPC::X13 : PPC::R2, + is64bit ? MVT::i64 : MVT::i32); + } + // If this is a lowered altivec predicate compare, CompareOpc is set to the // opcode number of the comparison. SDLoc dl(Op); -- cgit v1.2.3