From 85e4f5bcf6aac02fe77eda4ab1b4a22c40144d05 Mon Sep 17 00:00:00 2001 From: Kit Barton Date: Fri, 15 Nov 2019 15:48:34 -0600 Subject: [PowerPC] Rename DarwinDirective to CPUDirective (NFC) Summary: This patch renames the DarwinDirective (used to identify which CPU was defined) to CPUDirective. It also adds the getCPUDirective() method and replaces all uses of getDarwinDirective() with getCPUDirective(). Once this patch lands and downstream users of the getDarwinDirective() method have switched to the getCPUDirective() method, the old getDarwinDirective() method will be removed. Reviewers: nemanjai, hfinkel, power-llvm-team, jsji, echristo, #powerpc, jhibbits Reviewed By: hfinkel, jsji, jhibbits Subscribers: hiraditya, shchenz, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70352 --- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp') diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp index ad37e435fa3..380d7188852 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp @@ -554,7 +554,7 @@ bool PPCTTIImpl::isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, void PPCTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP) { - if (ST->getDarwinDirective() == PPC::DIR_A2) { + if (ST->getCPUDirective() == PPC::DIR_A2) { // The A2 is in-order with a deep pipeline, and concatenation unrolling // helps expose latency-hiding opportunities to the instruction scheduler. UP.Partial = UP.Runtime = true; @@ -580,7 +580,7 @@ bool PPCTTIImpl::enableAggressiveInterleaving(bool LoopHasReductions) { // on combining the loads generated for consecutive accesses, and failure to // do so is particularly expensive. This makes it much more likely (compared // to only using concatenation unrolling). - if (ST->getDarwinDirective() == PPC::DIR_A2) + if (ST->getCPUDirective() == PPC::DIR_A2) return true; return LoopHasReductions; @@ -650,7 +650,7 @@ unsigned PPCTTIImpl::getCacheLineSize() const { return CacheLineSize; // On P7, P8 or P9 we have a cache line size of 128. - unsigned Directive = ST->getDarwinDirective(); + unsigned Directive = ST->getCPUDirective(); if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 || Directive == PPC::DIR_PWR9) return 128; @@ -666,7 +666,7 @@ unsigned PPCTTIImpl::getPrefetchDistance() const { } unsigned PPCTTIImpl::getMaxInterleaveFactor(unsigned VF) { - unsigned Directive = ST->getDarwinDirective(); + unsigned Directive = ST->getCPUDirective(); // The 440 has no SIMD support, but floating-point instructions // have a 5-cycle latency, so unroll by 5x for latency hiding. if (Directive == PPC::DIR_440) -- cgit v1.2.3