From 280f7101e8c82ae7e09a71f439dbcce18f2e18fc Mon Sep 17 00:00:00 2001 From: Petar Jovanovic Date: Mon, 14 Dec 2015 17:57:33 +0000 Subject: [Power PC] llvm soft float support for ppc32 This is the second in a set of patches for soft float support for ppc32, it enables soft float operations. Patch by Strahinja Petrovic. Differential Revision: http://reviews.llvm.org/D13700 llvm-svn: 255516 --- llvm/lib/Target/PowerPC/PPCSubtarget.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'llvm/lib/Target/PowerPC/PPCSubtarget.h') diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.h b/llvm/lib/Target/PowerPC/PPCSubtarget.h index 105ceae4e36..a55c0d3a722 100644 --- a/llvm/lib/Target/PowerPC/PPCSubtarget.h +++ b/llvm/lib/Target/PowerPC/PPCSubtarget.h @@ -83,6 +83,7 @@ protected: bool Has64BitSupport; bool Use64BitRegs; bool UseCRBits; + bool UseSoftFloat; bool IsPPC64; bool HasAltivec; bool HasSPE; @@ -189,6 +190,8 @@ public: /// has64BitSupport - Return true if the selected CPU supports 64-bit /// instructions, regardless of whether we are in 32-bit or 64-bit mode. bool has64BitSupport() const { return Has64BitSupport; } + // useSoftFloat - Return true if soft-float option is turned on. + bool useSoftFloat() const { return UseSoftFloat; } /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit /// registers in 32-bit mode when possible. This can only true if -- cgit v1.2.3