From 5fde1b033e67bdc5d2df5f3423ed4c638ece61e6 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Fri, 5 Apr 2013 05:34:08 +0000 Subject: Add a SchedMachineModel for the PPC A2 llvm-svn: 178848 --- llvm/lib/Target/PowerPC/PPCScheduleA2.td | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'llvm/lib/Target/PowerPC/PPCScheduleA2.td') diff --git a/llvm/lib/Target/PowerPC/PPCScheduleA2.td b/llvm/lib/Target/PowerPC/PPCScheduleA2.td index ba63b5cd8fa..ae084aa0e8c 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleA2.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleA2.td @@ -749,3 +749,18 @@ def PPCA2Itineraries : ProcessorItineraries< [15, 7], [FPR_Bypass, FPR_Bypass]> ]>; + +// ===---------------------------------------------------------------------===// +// A2 machine model for scheduling and other instruction cost heuristics. + +def PPCA2Model : SchedMachineModel { + let IssueWidth = 1; // 2 micro-ops are dispatched per cycle. + let MinLatency = -1; // OperandCycles are interpreted as MinLatency. + let LoadLatency = 6; // Optimistic load latency assuming bypass. + // This is overriden by OperandCycles if the + // Itineraries are queried instead. + let MispredictPenalty = 6; + + let Itineraries = PPCA2Itineraries; +} + -- cgit v1.2.3