From 0f77861d9f25c8d5212a2cee7729a6c6e448864d Mon Sep 17 00:00:00 2001
From: Hal Finkel <hfinkel@anl.gov>
Date: Wed, 27 Mar 2013 06:52:27 +0000
Subject: Allocate r0 on PPC

The R0 register can now be allocated because instructions
that cannot use R0 as a GPR have been appropriately marked.

llvm-svn: 178123
---
 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 2 --
 1 file changed, 2 deletions(-)

(limited to 'llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp')

diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 0ebf1e8a418..b48305e9cf4 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -134,7 +134,6 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   Reserved.set(PPC::FP);
   Reserved.set(PPC::FP8);
 
-  Reserved.set(PPC::R0);
   Reserved.set(PPC::R1);
   Reserved.set(PPC::LR);
   Reserved.set(PPC::LR8);
@@ -150,7 +149,6 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   if (Subtarget.isPPC64()) {
     Reserved.set(PPC::R13);
 
-    Reserved.set(PPC::X0);
     Reserved.set(PPC::X1);
     Reserved.set(PPC::X13);
 
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