From 666323eacdf09fbd7b01719fb3fd7650b6188900 Mon Sep 17 00:00:00 2001 From: Dale Johannesen Date: Wed, 10 Oct 2007 01:01:31 +0000 Subject: Next PPC long double bits: ppcf128->i32 conversion. Surprisingly complicated. Adds getTargetNode for 2 outputs, no inputs (missing). llvm-svn: 42822 --- llvm/lib/Target/PowerPC/PPCISelLowering.h | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.h') diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h index 33f63814bc0..01a35a84553 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.h +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h @@ -129,7 +129,28 @@ namespace llvm { /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 /// or i32. - LBRX + LBRX, + + // The following 5 instructions are used only as part of the + // long double-to-int conversion sequence. + + /// OUTFLAG = MFFS F8RC - This moves the FPSCR (not modelled) into the + /// register. + MFFS, + + /// OUTFLAG = MTFSB0 INFLAG - This clears a bit in the FPSCR. + MTFSB0, + + /// OUTFLAG = MTFSB1 INFLAG - This sets a bit in the FPSCR. + MTFSB1, + + /// F8RC, OUTFLAG = FADDRTZ F8RC, F8RC, INFLAG - This is an FADD done with + /// rounding towards zero. It has flags added so it won't move past the + /// FPSCR-setting instructions. + FADDRTZ, + + /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR. + MTFSF }; } -- cgit v1.2.3