From 50d37a112974e32f19049fd07964c498bf9a29c3 Mon Sep 17 00:00:00 2001 From: Nemanja Ivanovic Date: Mon, 11 Dec 2017 14:35:48 +0000 Subject: [PowerPC] Sign-extend negative constant stores Second part of https://reviews.llvm.org/D40348. Revision r318436 has extended all constants feeding a store to 64 bits to allow for CSE on the SDAG. However, negative constants were zero extended which made the constant being loaded appear to be a positive value larger than 16 bits. This resulted in long sequences to materialize such constants rather than simply a "load immediate". This patch just sign-extends those updated constants so that they remain 16-bit signed immediates if they started out that way. llvm-svn: 320368 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.cpp') diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 3fe9fe73499..af2ea695089 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -12228,8 +12228,12 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, EVT VT = N->getOperand(1).getValueType(); if (Subtarget.isPPC64() && !DCI.isBeforeLegalize() && isa(N->getOperand(1)) && VT == MVT::i32) { - SDValue Const64 = DAG.getConstant(N->getConstantOperandVal(1), dl, - MVT::i64); + // Need to sign-extended to 64-bits to handle negative values. + EVT MemVT = cast(N)->getMemoryVT(); + uint64_t Val64 = SignExtend64(N->getConstantOperandVal(1), + MemVT.getSizeInBits()); + SDValue Const64 = DAG.getConstant(Val64, dl, MVT::i64); + // DAG.getTruncStore() can't be used here because it doesn't accept // the general (base + offset) addressing mode. // So we use UpdateNodeOperands and setTruncatingStore instead. -- cgit v1.2.3