From f67f3bf6270457fdbaf6ab50df41daf3996cc544 Mon Sep 17 00:00:00 2001
From: Nate Begeman <natebegeman@mac.com>
Date: Tue, 12 Apr 2005 07:04:16 +0000
Subject: Initial support for allocation condition registers

llvm-svn: 21246
---
 llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp')

diff --git a/llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp b/llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp
index ec25239721d..d8f008a1fea 100644
--- a/llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp
@@ -65,6 +65,14 @@ bool PPC32InstrInfo::isMoveInstr(const MachineInstr& MI,
     sourceReg = MI.getOperand(1).getReg();
     destReg = MI.getOperand(0).getReg();
     return true;
+  } else if (oc == PPC::MCRF) {             // mcrf cr1, cr2
+    assert(MI.getNumOperands() == 2 &&
+           MI.getOperand(0).isRegister() &&
+           MI.getOperand(1).isRegister() &&
+           "invalid PPC MCRF instruction");
+    sourceReg = MI.getOperand(1).getReg();
+    destReg = MI.getOperand(0).getReg();
+    return true;
   }
   return false;
 }
-- 
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