From ba532dc81648aca4cdf9ba4f5f16ecbc971e811c Mon Sep 17 00:00:00 2001 From: Kit Barton Date: Tue, 8 Mar 2016 03:49:13 +0000 Subject: [Power9] Implement new vsx instructions: load, store instructions for vector and scalar We follow the comments mentioned in http://reviews.llvm.org/D16842#344378 to implement this new patch. This patch implements the following vsx instructions: Vector load/store: lxv lxvx lxvb16x lxvl lxvll lxvh8x lxvwsx stxv stxvb16x stxvh8x stxvl stxvll stxvx Scalar load/store: lxsd lxssp lxsibzx lxsihzx stxsd stxssp stxsibx stxsihx 21 instructions Phabricator: http://reviews.llvm.org/D16919 llvm-svn: 262906 --- llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp') diff --git a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp index fd3c813acf4..6ea4fb1bfbc 100644 --- a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp +++ b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp @@ -368,6 +368,21 @@ static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm, return MCDisassembler::Success; } +static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm, + int64_t Address, const void *Decoder) { + // Decode the memrix16 field (imm, reg), which has the low 12-bits as the + // displacement with 16-byte aligned, and the next 5 bits as the register #. + + uint64_t Base = Imm >> 12; + uint64_t Disp = Imm & 0xFFF; + + assert(Base < 32 && "Invalid base register"); + + Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4))); + Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); + return MCDisassembler::Success; +} + static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { // The cr bit encoding is 0x80 >> cr_reg_num. -- cgit v1.2.3