From 4dc8fcc224aafb3394908618241dbf1b9a27a0c0 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Thu, 23 Apr 2015 23:16:22 +0000 Subject: [PowerPC] Support register name prefixes for vector registers Match binutils by supporting the optional register name prefix for new vector registers ("vs" for VSX registers and "q" for QPX registers). llvm-svn: 235665 --- llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp') diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp index 9492e1d3f66..b6f10e61079 100644 --- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp +++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp @@ -1219,10 +1219,18 @@ MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) { !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { RegNo = FRegs[IntVal]; return false; + } else if (Name.startswith_lower("vs") && + !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) { + RegNo = VSRegs[IntVal]; + return false; } else if (Name.startswith_lower("v") && !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { RegNo = VRegs[IntVal]; return false; + } else if (Name.startswith_lower("q") && + !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { + RegNo = QFRegs[IntVal]; + return false; } else if (Name.startswith_lower("cr") && !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) { RegNo = CRRegs[IntVal]; -- cgit v1.2.3