From d3f8fe81f47f0016dd9ebe79cb3061624086d00d Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Fri, 10 Feb 2012 04:10:36 +0000 Subject: RegAlloc superpass: includes phi elimination, coalescing, and scheduling. Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. llvm-svn: 150226 --- llvm/lib/Target/PTX/PTXRegAlloc.cpp | 7 +------ llvm/lib/Target/PTX/PTXTargetMachine.cpp | 2 ++ 2 files changed, 3 insertions(+), 6 deletions(-) (limited to 'llvm/lib/Target/PTX') diff --git a/llvm/lib/Target/PTX/PTXRegAlloc.cpp b/llvm/lib/Target/PTX/PTXRegAlloc.cpp index 2d2d5c30c8c..7fd53752bf6 100644 --- a/llvm/lib/Target/PTX/PTXRegAlloc.cpp +++ b/llvm/lib/Target/PTX/PTXRegAlloc.cpp @@ -24,10 +24,7 @@ namespace { class PTXRegAlloc : public MachineFunctionPass { public: static char ID; - PTXRegAlloc() : MachineFunctionPass(ID) { - initializePHIEliminationPass(*PassRegistry::getPassRegistry()); - initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry()); - } + PTXRegAlloc() : MachineFunctionPass(ID) {} virtual const char* getPassName() const { return "PTX Register Allocator"; @@ -35,8 +32,6 @@ namespace { virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesCFG(); - AU.addRequiredID(PHIEliminationID); - AU.addRequiredID(TwoAddressInstructionPassID); MachineFunctionPass::getAnalysisUsage(AU); } diff --git a/llvm/lib/Target/PTX/PTXTargetMachine.cpp b/llvm/lib/Target/PTX/PTXTargetMachine.cpp index 0432a8bcbd2..aac4555d020 100644 --- a/llvm/lib/Target/PTX/PTXTargetMachine.cpp +++ b/llvm/lib/Target/PTX/PTXTargetMachine.cpp @@ -319,6 +319,8 @@ bool PTXPassConfig::addCodeGenPasses(MCContext *&OutContext) { printAndVerify("After PreRegAlloc passes"); // Perform register allocation. + addPass(PHIEliminationID); + addPass(TwoAddressInstructionPassID); PM.add(createPTXRegisterAllocator()); printAndVerify("After Register Allocation"); -- cgit v1.2.3