From ca275d2a142f9aa4f375d361bcde6ffda00e182b Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Thu, 10 Apr 2014 13:16:49 +0000 Subject: [mips] Switch the MIPS-III and MIPS-IV assembler tests to use -mcpu=mips4. Summary: It is now the smallest superset for these ISA's. FeatureMips4 now contains FeatureFPIdx since [ls][dw]xc1 were added in MIPS-IV. Made the FPIdx feature bit lowercase so that it can be used in the -mattr option. Depends on D3274 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3275 llvm-svn: 205964 --- llvm/lib/Target/Mips/Mips.td | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'llvm/lib/Target/Mips') diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td index 10a469972f4..7a8198c150d 100644 --- a/llvm/lib/Target/Mips/Mips.td +++ b/llvm/lib/Target/Mips/Mips.td @@ -54,7 +54,7 @@ def FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true", "Enable 'byte/half swap' instructions.">; def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true", "Enable 'count leading bits' instructions.">; -def FeatureFPIdx : SubtargetFeature<"FPIdx", "HasFPIdx", "true", +def FeatureFPIdx : SubtargetFeature<"fpidx", "HasFPIdx", "true", "Enable 'FP indexed load/store' instructions.">; def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32", "Mips32 ISA Support", @@ -65,7 +65,7 @@ def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion", FeatureFPIdx]>; def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion", "Mips4", "MIPS IV ISA Support", - [FeatureGP64Bit, FeatureFP64Bit, + [FeatureGP64Bit, FeatureFP64Bit, FeatureFPIdx, FeatureCondMov]>; def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion", "Mips64", "Mips64 ISA Support", -- cgit v1.2.3