From b3e7ed3b941b3477b7797860eb99cb5154ba015e Mon Sep 17 00:00:00 2001 From: Stefan Maksimovic Date: Thu, 8 Feb 2018 09:25:17 +0000 Subject: [mips] Define certain instructions in microMIPS32r3 Instructions affected: mthc1, mfhc1, add.d, sub.d, mul.d, div.d, mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d These instructions are now defined for microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td since they shared their encoding with those already defined in microMIPS32r6InstrInfo.td and have been therefore removed from the latter file. Some instructions present in MicroMipsInstrFPU.td which did not have both AFGR64 and FGR64 variants defined have been altered to do so. Differential revision: https://reviews.llvm.org/D42738 llvm-svn: 324584 --- llvm/lib/Target/Mips/MipsRegisterInfo.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'llvm/lib/Target/Mips/MipsRegisterInfo.cpp') diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp index 0e0d82270c8..1f09ff1a6df 100644 --- a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp @@ -74,7 +74,9 @@ MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, case Mips::GPR64RegClassID: case Mips::DSPRRegClassID: { const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); - return 28 - TFI->hasFP(MF); + bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed() + ? TFI->hasFP(MF) : true; + return 28 - HasFP; } case Mips::FGR32RegClassID: return 32; -- cgit v1.2.3