From b976fee83c474bb8a295cf141ed0cfe3717a8fee Mon Sep 17 00:00:00 2001 From: Sasa Stankovic Date: Mon, 14 Jul 2014 09:40:29 +0000 Subject: [mips] Expand BuildPairF64 to a spill and reload when the O32 FPXX ABI is enabled and mthc1 and dmtc1 are not available (e.g. on MIPS32r1) This prevents the upper 32-bits of a double precision value from being moved to the FPU with mtc1 to an odd-numbered FPU register. This is necessary to ensure that the code generated executes correctly regardless of the current FPU mode. MIPS32r2 and above continues to use mtc1/mthc1, while MIPS-IV and above continue to use dmtc1. Differential Revision: http://reviews.llvm.org/D4465 llvm-svn: 212930 --- llvm/lib/Target/Mips/MipsMachineFunction.cpp | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'llvm/lib/Target/Mips/MipsMachineFunction.cpp') diff --git a/llvm/lib/Target/Mips/MipsMachineFunction.cpp b/llvm/lib/Target/Mips/MipsMachineFunction.cpp index e30302e0afd..a3306686fc4 100644 --- a/llvm/lib/Target/Mips/MipsMachineFunction.cpp +++ b/llvm/lib/Target/Mips/MipsMachineFunction.cpp @@ -137,4 +137,12 @@ MachinePointerInfo MipsFunctionInfo::callPtrInfo(const GlobalValue *Val) { return MachinePointerInfo(E); } +int MipsFunctionInfo::getBuildPairF64_FI(const TargetRegisterClass *RC) { + if (BuildPairF64_FI == -1) { + BuildPairF64_FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(), + RC->getAlignment(), false); + } + return BuildPairF64_FI; +} + void MipsFunctionInfo::anchor() { } -- cgit v1.2.3